A novel DSP‐based PFC‐DPLL with fuzzy controlled acquisition aid to improve acquisition performance and noise immunity

Abstract

SUMMARYThis paper proposes a new digital signal processing (DSP)-based phase frequency controlled digital phase locked loop. Here, a very simplistic form of fuzzy logic controller with the help of carrier phase and frequency error as input data is used to provide an acquisition aid. A frequency discriminator is employed to generate frequency error, and phase detector output is taken for phase error. This addition of an acquisition aid helps the loop to achieve the minimum acquisition time and maximum noise rejection simultaneously. An additional phase control in the digitally controlled oscillator makes the loop perform even better towards this goal. The implementation of the proposed loop is carried out on a reconfigurable logic platform using System Generator ® , a tool from Xilinx ® used to design real-time DSP application. A significant improvement of time domain characteristics are observed as well as the performance in presence of additive white Gaussian noise is demonstrated in terms of the reduction in steady-state phase jitter and enhancement in output signal to noise ratio in the proposed loop.

A new DSP based DPLL incorporates a dither signal and an additional phase control to overcome the deleterious effect of truncation error

“…In recent time, the advancement in digital signal processing (DSP) techniques and its related hardware, DSP based digital phase locked loop (DSP DPLL) are very popular in use [2,3]. These DSP based DPLLs are mainly carrier locking loops designed for running on digital signal processors where processing is done on sampled signals [4,5].…”

“…So, another change in the loop is proposed in terms of addition of a phase control in the DCO architecture [2,9]. After this addition, the DCO output phase along with frequency can be varied using input control voltage.…”