A Novel Fabrication Method for the Nanoscale Tunneling Field Effect Transistor

Abstract

Tunneling Field Effect Transistors (TFETs) are considered as a candidate for low power applications. However, most of TFETs have been researched on only for long channels due to the misalignment problem that occurs during the source/drain doping process in device fabrication. Thus, a new method is proposed for the fabrication of TFETs in nanoscale regions. This proposed fabrication process does not need an additional mask to define the source/drain regions, and makes it possible to form a self-aligned source/drain doping process. In addition, through TCAD simulation, the electrical characteristics of a TFET with dopant engineering and a rounded gate edge shape for a higher on/off current ratio were investigated. As a result, the TFET showed the properties of a larger on-current, a lower average subthreshold swing (58.5 mV/dec), and a 30-fold smaller leakage current compared to the conventional TFET The TFET with dopant engineering and a rounded gate edge shape can also be fabricated simply through the proposed fabrication process.

Complementary-Metal–Oxide–Semiconductor Technology-Compatible Tunneling Field-Effect Transistors with 14 nm Gate, Sigma-Shape Source, and Recessed Channel

“…# 2013 The Japan Society of Applied Physics placed on the same level using two-step sidewall image transfer technique. [15][16][17][18] This allows TFETs and MOSFETs to be co-integrated on the same level. As a result, there is no need for either forming buried contacts or wiring electrodes formed on different levels.…”

Reduction of ambipolar characteristics of vertical channel tunneling field-effect transistor by using dielectric sidewall

“…In the conventional planar channel TFETs, source drain alignment induces additional patterning process for asymmetric doping in source and drain. To solve the alignment problem in plane type TFET, previous work with modified fabrication process was presented [12]. Similar with the previous work, vertical channel uses the source region as an implantation mask for the drain region.…”

Hole-Effective Masses in the Transport Calculation of Si Nanowire pMOSFETs

“…[1][2][3] On the other hand, for p-type nanowire devices, the PEM model does not correctly produce the valence subbands that are in fact dictated by the strong coupling of the confined heavy and light holes. Thus, the validity and the limitations of the PEM model with respect to its application to the transport problem is not known, other than a general speculation that the PEM model in the p-type device would not work as well as it does for the n-type counterpart.…”