A novel field programmable gate array architecture for high speed arithmetic processing

Miller, Nory; Quigley, Steven F.

doi:10.1007/bfb0055266

Cited by 3 publications

(2 citation statements)

References 4 publications

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“…The reconfigurable arithmetic FPGA (RA-FPGA) [32] is an arithmetic array partitioned into three regions: 1) two's complement addition; 2) sign/magnitude conversion to two's complement, and vice versa; and 3) multiplication and division. Traditional FPGA-style logic is also included in order to implement control and general-purpose logic.…”

Section: Programmable Arrays Of Arithmetic Primitivesmentioning

confidence: 99%

Improving FPGA Performance for Carry-Save Arithmetic

Parandeh-Afshar

Verma

Brisk

et al. 2010

IEEE Trans. VLSI Syst.

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Abstract-The selective use of carry-save arithmetic, where appropriate, can accelerate a variety of arithmetic-dominated circuits. Carry-save arithmetic occurs naturally in a variety of DSP applications, and further opportunities to exploit it can be exposed through systematic data flow transformations that can be applied by a hardware compiler. Field-programmable gate arrays (FPGAs), however, are not particularly well suited to carry-save arithmetic. To address this concern, we introduce the "field programmable counter array" (FPCA), an accelerator for carry-save arithmetic intended for integration into an FPGA as an alternative to DSP blocks. In addition to multiplication and multiply accumulation, the FPCA can accelerate more general carry-save operations, such as multi-input addition (e.g., add 2 integers) and multipliers that have been fused with other adders. Our experiments show that the FPCA accelerates a wider variety of applications than DSP blocks and improves performance, area utilization, and energy consumption compared with soft FPGA logic.Index Terms-Carry-save arithmetic, field-programmable gate array (FPGA), generalized parallel counter (GPC).

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Section: Programmable Arrays Of Arithmetic Primitivesmentioning

confidence: 99%

Improving FPGA Performance for Carry-Save Arithmetic

Parandeh-Afshar

Verma

Brisk

et al. 2010

IEEE Trans. VLSI Syst.

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“…Dependent on the amount of the dedicated logic resources and their overall organization, FPGA architectures of this kind have either a homogeneous structure (all logic blocks are DSP-optimized) [1] or are heterogeneous (an FPGA is divided into regions with DSP-optimized and general-purpose cells) [6]. The third group includes hybrid FPGA architectures which are globally homogeneous and locally heterogeneous (an FPGA has either a hierarchical structure with a heterogeneous lowest level [12], or each FPGA cell has mixed-type components [18]). …”

Section: Previous Workmentioning

confidence: 99%

An FPGA architecture with enhanced datapath functionality

Leijten-Nowak

Meerbergen

2003

Proceedings of the 2003 ACM/SIGDA Eleventh International Symposium on Field Programmable Gate Arrays

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Although FPGAs are a cost-efficient alternative for both ASICs and general purpose processors, they still result in designs which are more than an order of magnitude more costly and slower than their equivalents implemented in dedicated logic. This efficiency gap makes FPGAs less suitable for high-volume cost-sensitive applications (e.g. embedded systems).We show that the intrinsic cost of traditional general-purpose FPGAs can be reduced if they are designed to target an application domain or a class of applications only. We propose a method of the application-domain characterization and apply it to characterize DSP. A novel FPGA logic block architecture derived based on such an analysis, and which exploits properties of target applications, is presented. Its key feature is the 'mixed-level granularity' being a trade-off between fine and coarse granularity required for the implementation of datapath and random logic functions, respectively. This leads to a factor of four improvement in the LUT memory size compared to commercial FPGAs, and, assuming a standardcell implementation, a 1.6-2.8 lower datapath mapping cost. A modified mixed-grain architecture with the ALU-like functionality reduces the LUT memory size by a factor of 16 compared to commercial FPGAs, and mapped onto standard cells has a 1.9-3.3 times higher datapath mapping efficiency. For these reasons, the proposed FPGA architectures may be an interesting alternative to the traditional general-purpose FPGA devices, especially if characteristics of a target application domain are known a priori.

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Configurable arithmetic arrays with data-driven control

Parhami

Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers (Cat. No.00CH37154)

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A novel field programmable gate array architecture for high speed arithmetic processing

Cited by 3 publications

References 4 publications

Improving FPGA Performance for Carry-Save Arithmetic

Improving FPGA Performance for Carry-Save Arithmetic

An FPGA architecture with enhanced datapath functionality

Configurable arithmetic arrays with data-driven control

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