An FPGA architecture with enhanced datapath functionality

Abstract

Although FPGAs are a cost-efficient alternative for both ASICs and general purpose processors, they still result in designs which are more than an order of magnitude more costly and slower than their equivalents implemented in dedicated logic. This efficiency gap makes FPGAs less suitable for high-volume cost-sensitive applications (e.g. embedded systems).We show that the intrinsic cost of traditional general-purpose FPGAs can be reduced if they are designed to target an application domain or a class of applications only. We propose a method of the application-domain characterization and apply it to characterize DSP. A novel FPGA logic block architecture derived based on such an analysis, and which exploits properties of target applications, is presented. Its key feature is the 'mixed-level granularity' being a trade-off between fine and coarse granularity required for the implementation of datapath and random logic functions, respectively. This leads to a factor of four improvement in the LUT memory size compared to commercial FPGAs, and, assuming a standardcell implementation, a 1.6-2.8 lower datapath mapping cost. A modified mixed-grain architecture with the ALU-like functionality reduces the LUT memory size by a factor of 16 compared to commercial FPGAs, and mapped onto standard cells has a 1.9-3.3 times higher datapath mapping efficiency. For these reasons, the proposed FPGA architectures may be an interesting alternative to the traditional general-purpose FPGA devices, especially if characteristics of a target application domain are known a priori.

Using bus-based connections to improve field-programmable gate array density for implementing datapath circuits

“…Several multi-bit FPGA architectures have been proposed in the past [1]- [12] with a wide range of routing architecture designs; and, in this work, we focus on the problem of incorporating busbased connections into segmented-style routing resources [13]. In particular, we propose a specific routing architecture, called the multi-bit routing architecture, and empirically evaluate its area efficiency.…”

Floating-Point FPGA: Architecture and Modeling

“…Leijten-Nowak and van Meerbergen [7] proposed mixedlevel granularity logic blocks and compared their benefits with a standard island-style FPGA using the VPR tool [1]. Ye et al [8] studied the effects of coarse-grained logic cells (LCs) and routing resources for datapath circuits, also using VPR.…”

A novel FPGA logic block for improved arithmetic performance

“…Kuon and Rose [19] have recently shown that hard, hand-optimized IP cores-namely DSP and MAC blocks-do not offer tangible performance advantages due to the high cost of routing data to and from these blocks, and mismatches in bitwidth. Previous enhancements to FPGA logic blocks, such as support for binary and ternary addition [1,3,40,41] and carry-chains [8,12,14,18,21], have improved FPGA performance for arithmetic operations. Nonetheless, the performance gap between ASICs and FPGAs remains.…”