Floating-Point FPGA: Architecture and Modeling

Ho, Chun Hok; Yu, Chun‐Yen; Leong, Philip H. W.; Luk, Wayne; Wilton, Steven J. E.

doi:10.1109/tvlsi.2008.2006616

Cited by 50 publications

(3 citation statements)

References 14 publications

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“…Other computer algorithms implemented in FPGAs described in this review includes CORDIC [1645][1646][1647], floating point [831,1648,1649], distributed arithmetic [1650,1651] and so on. Similarly, other implementations techniques for FPGAs found here were PWM [890,1652,1653], finite state machines [1654][1655][1656], scheduling [1657][1658][1659][1660], cellular automata [924,932], PLLs [950,1661,1662], ring oscillators [339, 962,1663], and so forth.…”

Section: Discussionmentioning

confidence: 99%

Field Programmable Gate Array Applications—A Scientometric Review

2019

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Field Programmable Gate Array (FPGA) is a general purpose programmable logic device that can be configured by a customer after manufacturing to perform from a simple logic gate operations to complex systems on chip or even artificial intelligence systems. Scientific publications related to FPGA started in 1992 and, up to now, we found more than 70,000 documents in the two leading scientific databases (Scopus and Clarivative Web of Science). These publications show the vast range of applications based on FPGAs, from the new mechanism that enables the magnetic suspension system for the kilogram redefinition, to the Mars rovers’ navigation systems. This paper reviews the top FPGAs’ applications by a scientometric analysis in ScientoPy, covering publications related to FPGAs from 1992 to 2018. Here we found the top 150 applications that we divided into the following categories: digital control, communication interfaces, networking, computer security, cryptography techniques, machine learning, digital signal processing, image and video processing, big data, computer algorithms and other applications. Also, we present an evolution and trend analysis of the related applications.

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Section: Discussionmentioning

confidence: 99%

Field Programmable Gate Array Applications—A Scientometric Review

2019

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“…One alternative is to integrate floating-point units as hard blocks [2,5,9]; however, applications that are not floating-point intensive will be unable to use these blocks. To date, FPGA vendors do not sell device families with dedicated blocks for floating-point applications.…”

Section: Related Workmentioning

confidence: 99%

Reducing the cost of floating-point mantissa alignment and normalization in FPGAs

Moctar

George

Parandeh-Afshar

et al. 2012

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays

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In floating-point datapaths synthesized on FPGAs, the shifters that perform mantissa alignment and normalization consume a disproportionate number of LUTs. Shifters are implemented using several rows of small multiplexers; unfortunately, multiplexerbased logic structures map poorly onto LUTs. FPGAs, meanwhile, contain a large number of multiplexers in the programmable routing network; these multiplexer are placed under static control of the FPGA's configuration bitstream. In this work, we modify some of the routing multiplexers in the intracluster routing network of a CLB in an FPGA to implement shifters for floating-point mantissa alignment and normalization; the number of CLBs required for these operations is reduced by 67%. If shifting is not required, the routing multiplexers that have been modified can be configured to operate as normal routing multiplexers, so no functionality is sacrificed. The area overhead incurred by these modifications is small, and there is no need to modify every routing multiplexer in the FPGA. Experiments show that there is no negative impact in terms of clock frequency or routability for benchmarks that do not use the dynamic multiplexers.

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“…Thus, some requirements of this standard may not match the typical characteristics of FPGA devices. A more efficient implementation of FP arithmetic for FPGAs could be achieved if the architecture was defined taking into account the resources available in FPGA devices [2,4,9] For instance, FP addition involves two variable shifters and a leading zero detector (for alignment and normalization), which are very slow when they are implemented in FPGAs. If the maximum number of digits to be shifted is reduced, the penalty due to this operation also decreases.…”

Section: Introductionmentioning

confidence: 99%

High-Radix Formats for Enhancing Floating-Point FPGA Implementations

Villalba

Hormigo

2021

Circuits Syst Signal Process

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This article proposes a family of high-radix floating-point representation to efficiently deal with floating-point addition in FPGA devices with no native floating-point support. Since variable shifter implementation (required in any FP adder) has a very high cost in FPGA, high-radix formats considerably reduce the number of possible shifts, decreasing the execution time and area highly. Although the high-radix format produces also a significant penalty in the implementation of multipliers, the experimental results show that the adder improvement overweights the multiplication penalty for most of the practical and common cases (digital filters, matrix multiplications, etc.). We also provide the designer with guidelines on selecting a suitable radix as a function of the ratio between the number of additions and multiplications of the targeted algorithm. For applications with similar numbers of additions and multiplications, the high-radix version may be up to 26% faster and even having a wider dynamic range and using higher number of significant bits. Furthermore, thanks to the proposed efficient converters between the standard IEEE-754 format and our internal high-radix format, the cost of the input/output conversions in FPGA accelerators is negligible.

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Floating-Point FPGA: Architecture and Modeling

Cited by 50 publications

References 14 publications

Field Programmable Gate Array Applications—A Scientometric Review

Field Programmable Gate Array Applications—A Scientometric Review

Reducing the cost of floating-point mantissa alignment and normalization in FPGAs

High-Radix Formats for Enhancing Floating-Point FPGA Implementations

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