A Novel FinFET With High-Speed and Prolonged Retention for Dynamic Memory

Moon, Dong‐Il; Kim, Jee-Yeon; Jang, Hyung Wook; Hong, Hee-Jeong; Kim, Choong Ki; Oh, Jin Kyung; Kang, Min-Ho; Kim, Jeoung-Woo; Choi, Yang‐Kyu

doi:10.1109/led.2014.2365235

Cited by 17 publications

(3 citation statements)

References 8 publications

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“…Finally, the conventional furnace based 1 st FGA with H 2 was applied to all the devices before evaluating the three annealing methods. Details of the fabrication process flow, and additional transmission electron microscope (TEM) images for along the gate as well as along the channel and gate oxide thickness, have already been reported in our previous works [7], [16].…”

Section: Methodsmentioning

confidence: 99%

A Comparative Study of the Curing Effects of Local and Global Thermal Annealing on a FinFET

Park

Lee

Choi

2019

IEEE J. Electron Devices Soc.

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Recently, localized thermal annealing has been spotlighted as an effective method to cure aged devices. The degraded gate oxide can be successfully cured by local annealing, which utilizes Joule heat inherently generated in the device. But, despite this advantage, there has been no study comparing the curing effects with various other annealing methods. In this study, the curing effects of local annealing and a conventional global annealing method applied to SOI FinFETs are compared. The measured electrical characteristics are discussed to evaluate the damage curing with respect to curing level and variability.INDEX TERMS Damage curing, degradation, electrothermal annealing (ETA), FinFET, forming gas annealing (FGA), global annealing, hot-carrier injection (HCI), Joule heat, local annealing, reliability, SOI FinFET.

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Section: Methodsmentioning

confidence: 99%

A Comparative Study of the Curing Effects of Local and Global Thermal Annealing on a FinFET

Park

Lee

Choi

2019

IEEE J. Electron Devices Soc.

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“…SiNW FETs was fabricated on a p-type silicon-on-insulator (SOI) wafer [17]. The thickness of top silicon was reduced to 50 nm by iterative thermal oxidation and diluted HF dipping.…”

Section: Methodsmentioning

confidence: 99%

Feasibility Study of Extended-Gate-Type Silicon Nanowire Field-Effect Transistors for Neural Recording

Kang

Kim

Choi

et al. 2017

Sensors

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In this research, a high performance silicon nanowire field-effect transistor (transconductance as high as 34 µS and sensitivity as 84 nS/mV) is extensively studied and directly compared with planar passive microelectrode arrays for neural recording application. Electrical and electrochemical characteristics are carefully characterized in a very well-controlled manner. We especially focused on the signal amplification capability and intrinsic noise of the transistors. A neural recording system using both silicon nanowire field-effect transistor-based active-type microelectrode array and platinum black microelectrode-based passive-type microelectrode array are implemented and compared. An artificial neural spike signal is supplied as input to both arrays through a buffer solution and recorded simultaneously. Recorded signal intensity by the silicon nanowire transistor was precisely determined by an electrical characteristic of the transistor, transconductance. Signal-to-noise ratio was found to be strongly dependent upon the intrinsic 1/f noise of the silicon nanowire transistor. We found how signal strength is determined and how intrinsic noise of the transistor determines signal-to-noise ratio of the recorded neural signals. This study provides in-depth understanding of the overall neural recording mechanism using silicon nanowire transistors and solid design guideline for further improvement and development.

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“…Such a device composed of gate s ilicon-blocking o xide-charge trap n itride-channel s ilicon can be abbreviated as SONS. Although the SONS device has short-term memory properties akin to a dynamic random-access memory (DRAM) device, it does not lose the characteristic of multiple memory states, similar to SONOS-based flash memory. , Owing to the three-terminal structure that allows write operations in the off-state, the power consumption to encode temporal inputs and to generate reservoir states is reduced. In addition, 4-bit reservoir operation is confirmed with the use of the fabricated L-FinFET reservoirs, and pattern recognition is conducted by dividing an entire image into many rows of pixels whose allocated values correspond to a sequential input to the reservoir.…”

Section: Introductionmentioning

confidence: 99%

Leaky FinFET for Reservoir Computing with Temporal Signal Processing

Han

Yun

et al. 2023

ACS Appl. Mater. Interfaces

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Reservoir computing can greatly reduce the hardware and training costs of recurrent neural networks with temporal data processing. To implement reservoir computing in a hardware form, physical reservoirs transforming sequential inputs into a high-dimensional feature space are necessary. In this work, a physical reservoir with a leaky fin-shaped field-effect transistor (L-FinFET) is demonstrated by the positive use of a short-term memory property arising from the absence of an energy barrier to suppress the tunneling current. Nevertheless, the L-FinFET reservoir does not lose its multiple memory states. The L-FinFET reservoir consumes very low power when encoding temporal inputs because the gate serves as an enabler of the write operation, even in the off-state, due to its physical insulation from the channel. In addition, the small footprint area arising from the scalability of the FinFET due to its multiple-gate structure is advantageous for reducing the chip size. After the experimental proof of 4-bit reservoir operations with 16 states for temporal signal processing, handwritten digits in the Modified National Institute of Standards and Technology dataset are classified by reservoir computing.

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A Novel FinFET With High-Speed and Prolonged Retention for Dynamic Memory

Cited by 17 publications

References 8 publications

A Comparative Study of the Curing Effects of Local and Global Thermal Annealing on a FinFET

A Comparative Study of the Curing Effects of Local and Global Thermal Annealing on a FinFET

Feasibility Study of Extended-Gate-Type Silicon Nanowire Field-Effect Transistors for Neural Recording

Leaky FinFET for Reservoir Computing with Temporal Signal Processing

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