A Novel Flit Serialization Strategy to Utilize Partially Faulty Links in Networks-on-Chip

Abstract

Abstract-Aggressive MOS transistor size scaling substantially increase the probability of faults in NoC links due to manufacturing defects, process variations, and chip wire-out effects. Strategies have been proposed to tolerate faulty wires by replacing them with spare ones or by partially using the defective links. However, these strategies either suffer from high area and power overheads, or significantly increase the average network latency. In this paper, we propose a novel flit serialization method, which divides the links and flits into several sections, and serializes flit sections of adjacent flits to transmit them on all available fault-free link sections to avoid the complete waste of defective links bandwidth. Experimental results indicate that our method reduces the latency overhead significantly and enables graceful performance degradation, when compared with related partially faulty link usage proposals, and saves area and power overheads by up to 29% and 43.1%, respectively, when compared with spare wire replacement methods.

Variable-width datapath for on-chip network static power reduction

“…To increase a channel's tolerance to silicon defects, spare channel bits can be associated with every channel [10,52,25]. Other mechanisms use channels with defects partially by serializing and deserializing flits [39,7]. Past work also uses bidirectional channels to avoid costly detours in the presence of faults [47].…”