A novel functional test generation method for processors using commercial ATPG

Abstract

As the sizes of general and special purpose proctwors increase rapidly, generating high quality manufacturing tests for them is becoming a serious problem in industry. This paper describes a novel method for hierarchical functional test generation for processors which turgets one embedded module at a time and uses commm-cia1 ATPG tools to derive tests for faults within the module. Applying the technique to benchmark processor designs, we were able to obtain test eficiencies for the embedded modules of the processors which were extremely close to what the commercial ATPG could do with complete access to the module. The hierarchical approach used produced this result, using the same comme,rcial tool, but required a CPU time several orders of magnitude less than when using a conventional, flat view of the circuit.INrERblATIONAL TEST CONFERENCE 0-78034209-7/97 $1 0.00 0 1997 IEEE Paper 30.3 743

Automatic Test Program Generation for Out-of-Order Superscalar Processors

“…At this point, the second pair of LD instructions has to wait since there are no available channels. In the fourth cycle C 4 , head moves to the 3 rd cell. The second pair of LD instructions is issued and the third pair of LD instructions has to wait.…”

“…Later, a more scalable SBST technique [3] was presented for more complex processors. It applied statistical regression to extract instruction-level constraints for constrained ATPG (CATPG) [4]. In an effort to achieve more efficiency than CATPG, learning methods [5] have been used to deduce, based on simulation runs, relations between instructions, I/O data and component signals.…”

Software-Based Self-Testing of Processors Using Expanded Instructions

“…The first functional test method for processors was proposed in [5] [6], which considers functional fault models instead of structural fault models. Then an automatic test generation method was presented for functional testing of gate-level components [7], which extracts functional constraints with FALCON [8], models these constraints as virtual circuits on component ports, and applies automatic test pattern generation (ATPG) on the constrained components. Later, a structural SBST method was presented in [3] to testing structural faults on processors, which applies instructions to generate random test patterns onchip, called random pattern based SBST (RSBST) in this work.…”

Using RT Level Component Descriptions for Single Stuck-at Hierarchical Fault Simulation

“…This problem has forced design and test methodologies to use higher levels of description for the circuits under test [9,10,12,17,20,22,25]. Some methods use higher levels of abstraction to apply fault simulation to general modules [6], while others use higher abstraction levels in a rather static manner with a gatelevel description [18].…”