As the sizes of general and special purpose proctwors increase rapidly, generating high quality manufacturing tests for them is becoming a serious problem in industry. This paper describes a novel method for hierarchical functional test generation for processors which turgets one embedded module at a time and uses commm-cia1 ATPG tools to derive tests for faults within the module. Applying the technique to benchmark processor designs, we were able to obtain test eficiencies for the embedded modules of the processors which were extremely close to what the commercial ATPG could do with complete access to the module. The hierarchical approach used produced this result, using the same comme,rcial tool, but required a CPU time several orders of magnitude less than when using a conventional, flat view of the circuit.INrERblATIONAL TEST CONFERENCE 0-78034209-7/97 $1 0.00 0 1997 IEEE Paper 30.3 743

This paper describes a novel method for hierarchical functional test generation for processors. This method targets one embedded module at a time and uses commercial ATPG tools to derive tests for faults within the module. Since the commercial tools are unable to deal with the entire design, functional constraints are first extracted for the module. The extracted constraints are described in VerilogNHDL and synthesized to the gate level. Then a commercial sequential ATPG is used to generate module level test vectors for faults within the module. Finally, these module level vectors are translated to processor level functional vectors and fault simulated to verify that the same coverage is obtained. Applying the technique to a benchmark processor design, we were able to obtain a test efficiency for the embedded ALU of the processor which was extremely close to what the commercial ATPG could do with complete access to the module. IntroductionAs the sizes of general and special purpose processors increase rapidly, generating high quality manufacturing tests for them is becoming a serious problem. In this paper we describe a hierarchical functional vector generation using ATPG.We describe a revolutionary method for functional test generation for an embedded module, which uses a gate level sequential ATPG to detect all the detectable faults under the functional constraints. Functional constraints are divided into control, data, state and output constraints. The extracted constraints are described in VerilogNHDL and synthesized to gates. Then a commercial sequential ATPG is used to generate module level vectors. These module level vectors are translated to processor level functional vectors and fault simulated to verify that the 0-8186-7755-4/96 $05.00 0 1996 IEEE

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As the sizes of general and special purpose processors increase rapidly, generating high quality manufacturing tests which can be run at native speeds is becoming a serious problem. One solution is a novel method for functional test generation in which a transformed m o dule is built manually, and which embodies functional constraints described using virtual logic. Test generation is then performed on the transformed m o dule using commercial tools and the transformed module patterns are t r anslated b ack to the processor level. However, the technique is useful only if the virtual logic can be generated automatically. This paper describes an automatic functional constraint extraction algorithm and a procedure to build the transformed module. We describe the tool, FALCON, used to extract the functional constraints of a given embedded m o dule fro m a V erilog R TL model. The constraint extraction for embedded m o dules of benchmark processors using FALCON takes only a few seconds. We show that this method can generate functional patterns in a time several orders of magnitude less than one using a conventional, at view of the circuit.

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