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As the sizes of general and special purpose processors increase rapidly, generating high quality manufacturing tests which can be run at native speeds is becoming a serious problem. One solution is a novel method for functional test generation in which a transformed m o dule is built manually, and which embodies functional constraints described using virtual logic. Test generation is then performed on the transformed m o dule using commercial tools and the transformed module patterns are t r anslated b ack to the processor level. However, the technique is useful only if the virtual logic can be generated automatically. This paper describes an automatic functional constraint extraction algorithm and a procedure to build the transformed module. We describe the tool, FALCON, used to extract the functional constraints of a given embedded m o dule fro m a V erilog R TL model. The constraint extraction for embedded m o dules of benchmark processors using FALCON takes only a few seconds. We show that this method can generate functional patterns in a time several orders of magnitude less than one using a conventional, at view of the circuit.

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