Effects of multi-cycle sensitization on delay tests

Krishnamachary, Arun; Abraham, Jacob A.

doi:10.1109/icvd.2003.1183127

Cited by 4 publications

(2 citation statements)

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“…There exist two delay fault models: path delay faults and gate delay faults, here we use path delay faults. So far, the test of delay faults is studied intensively [9,10]. Chakradhar et al presented an effective approach that formulates delay test generation as energy function minimization problem [11], this extends the previous results [3,5] on stuck-at faults to delay faults.…”

Section: An Energy Model For Delay Faults Testingmentioning

confidence: 95%

Neural network model for testing stuck-at and delay faults in digital circuit

Zhang

Proceedings. 17th International Conference on VLSI Design

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The automatic test pattern generation techniques using artificial neural networks are studied. First, an optimal neural network model of digital circuits is investigated. The network model can represent a logic circuit by the minimal number of neurons. It is shown that there exist optimal neural networks for arbitrary logic circuits. We can get the network parameters by solving a system of linear equations. Second, a new energy model for delay faults testing of digital circuits is presented, which is based on the optimal neural network models. Third, it is shown that the test generation approach using the optimal neural network model can reduce the search space, and has better computation efficiency if compared with the circuit test methods using Hopfield binary neural network.

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Section: An Energy Model For Delay Faults Testingmentioning

confidence: 95%

Neural network model for testing stuck-at and delay faults in digital circuit

Zhang

Proceedings. 17th International Conference on VLSI Design

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“…This gives rise to a greater test time with LOC [12]. Since the initialization pattern, being loaded through scan, might not be a valid state of the circuit, even LOC can detect faults which can be proven redundant under a greater sequential depth [17]. However, since LOC restricts the number of redundant transition faults that are tested, its use has been popular.…”

Section: Launch Off Capture (Loc)mentioning

confidence: 99%

Multi-Cycle Sensitizable Transition Delay Faults

Abraham

Goel

Kumar

24th IEEE VLSI Test Symposium

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Transition fault testing has been traditionally performed on full scan sequential circuits using a two vector test; the first vector is used to initialize a node while the second vector is used to sensitize the fault on the node and to propagate the fault effects to an observation point. Although a two pattern test is good for detecting most of the delay faults that can cause circuits to malfunction, there are certain delay defects that cannot be detected using this test generation approach. In this paper, we review this class of delay faults which require three or more vectors for their detection. We show how launch-off-shift (LOS) transition fault patterns can be used effectively to detect some of these faults thus improving the quality of the delay fault tests. We also explore methods to minimize the yield loss incurred on account of using LOS patterns. Delay fault detection in full-scan designsFor scan circuits, different methodologies are used for testing delay faults, the popular ones being -Enhanced Proceedings of the 24th IEEE VLSI Test Symposium (VTS'06) 0-7695-2514-8/06 $20.00

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