Path coverage based functional test generation for processor marginality validation

Natarajan, Suriyaprakash; Krishnamachary, Arun; Chiprout, Eli; Galivanche, Rajesh

doi:10.1109/test.2010.5699257

Cited by 8 publications

(1 citation statement)

References 21 publications

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“…Delay faults in deep submicron are one of the primary reasons of system failure and need to be detected [43]. At-speed functional testing is one of the well-known methods to detect delay faults [44] and we are going to use this technique in our NoC testing approach.…”

Section: Delay Fault Modelmentioning

confidence: 99%

At-Speed Distributed Functional Testing to Detect Logic and Delay Faults in NoCs

Kakoee

Bertacco

Benini

2014

IEEE Trans. Comput.

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Abstract-In this work, we propose a distributed functional test mechanism for NoCs which scales to large-scale networks with general topologies and routing algorithms. Each router and its links are tested using neighbors in different phases. The router under test is in test mode while all other parts of the NoC are operational. We use triple module redundancy (TMR) for the robustness of all testing components that are added into the switch. Experimental results show that our functional test approach can detect stuck-at, short and delay faults in the routers and links. Our approach achieves 100 percent stuck-at fault coverage for the data path and 85 percent for the control paths including routing logic, FIFO's control path, and the arbiter of a 5 Â 5 router. We also show that our approach is able to detect delay faults in critical control and data paths. Synthesis results show that the area overhead of our test components with TMR support is 20 percent for covering stuck-at, delay, and short-wire faults and 7 percent for covering only stuck-at and delay faults in the 5 Â 5 router. Simulation results show that our online testing approach has an average latency overhead of 3 percent in PARSEC traffic benchmarks on an 8 Â 8 NoC.

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Section: Delay Fault Modelmentioning

confidence: 99%