A novel hierarchical test generation method for processors

Tupuri, R.S.; Abraham, Jacob A.

doi:10.1109/icvd.1997.568203

Cited by 5 publications

(2 citation statements)

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“…In this way, faults are modeled on one level and after the synthesis the faults are mapped back. Such a hierarchical test generation method is proposed by Tupuri et al [26]. Test cases are generated for faults using commercial ATPGs for individual modules.…”

Section: Test Levelmentioning

confidence: 99%

Automated Test Case Generation for Digital System Designs: A Mapping Study on VHDL, Verilog, and SystemVerilog Description Languages

Vivekananda

Enoiu

2020

Designs

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Researchers have proposed different methods for testing digital systems and circuits in the last couple of decades. The need for testing digital logic circuits has become more important than ever due to the growing complexity of such systems. During the design phase, testing is focusing on design defects, as well as manufacturing and wear out type of defects. Failures in digital systems could be caused, for example, by design errors, the use of inherently probabilistic devices, and manufacturing variability. As a way to test digital systems in a more efficient way, automated test generation has been proposed to automatically create tests that can quickly and accurately identify faulty components. Examples of such techniques are the sequential test generation, the scan path testing, and the random test generation techniques. With the research domain becoming more mature and growing, it is essential to systematically identify, analyze, and classify these contributions. We performed a systematic mapping study of automated test generation for digital circuits aimed at providing an overview of the application of these techniques. We focused on three of the most widely-used and well-supported hardware description languages (HDLs) for digital systems: Verilog, SystemVerilog, and VHDL. Our results suggest that the majority of the test generation methods for digital circuits are focused on the behavioral and register-transfer design levels. Fault-independent and fault-oriented test generation are the most frequently reported types of test generation methods, while HDL model simulation is the most common test generation technology used to search for test cases in these academic studies. While the results are suggesting a growing interest in this area, the majority of articles are published as conferences papers. Our results show that only 31% of the methods are implemented as software tools and only 63% of all contributions are actually generating executable test cases. This study makes three important contributions, (i) a state-of-the-art of test generation for digital system designs research is provided, (ii) the reported characteristics are identified in both the primary papers and experimental reports, (iii) gaps and opportunities for future test generation for digital system designs research are identified.

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Section: Test Levelmentioning

confidence: 99%

Automated Test Case Generation for Digital System Designs: A Mapping Study on VHDL, Verilog, and SystemVerilog Description Languages

Vivekananda

Enoiu

2020

Designs

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“…Commercial ATPG tools can then be used to generate test patterns of the modules with the extracted constraints. The patterns are then translated into instructions [12]- [15]. For the random pattern generation, several methodologies have been developed [16] [17] [18].…”

Section: Introductionmentioning

confidence: 99%

A hybrid software-based self-testing methodology for embedded processor

Chen

Lee

2008

Proceedings of the 2008 ACM Symposium on Applied Computing

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Software-based self-test (SBST) is emerging as a promising technology for enabling at-speed testing of high-speed embedded processors testing in an SoC system. For SBST, test routine development or generation can base on deterministic and random methodology. The deterministic test methodology develops the test program for a pipeline processor using the information abstracted from its architecture model, RTL descriptions, and gate-level net-list for different types of processor circuits. The random test methodology tries to make the pseudo-exhaustive testing possible using random instructions or patterns. The proposed methodology improves coverage for structural faults using both deterministic and random development of the test code. Not only can the deterministic test program test lots of faults using very small code size, but also the random test program can help detect some of the faults that the deterministic test program is difficult to test. We demonstrated the feasibility of the proposed methodology by the achieved fault coverage, test program size, and testing cycle count on a complex pipeline processor core. Comparisons with previous work are also made. Experimental results show its potential as an effective method for practical use.

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On statistical behavior of branch coverage in testing behavioral VHDL models

Hajjar

Chen

Mayrhauser

Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786)

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During behavioral model verification, it is important to determine the stopping pointfor the current test strategy and for moving to a different test strategy. It has been shown that the location of the stopping point is highly dependent on the statistical model one should choose to describe the coverage behavior during the verification process. This paper presents a study on the coverage behavior of VHDL models. The resulting statistical behavior is compared to the statistical behavior used by some commonly used models for software reliability and shows the inappropriateness of applying the existing models for the behavior model verification.

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A novel hierarchical test generation method for processors

Cited by 5 publications

References 0 publications

Automated Test Case Generation for Digital System Designs: A Mapping Study on VHDL, Verilog, and SystemVerilog Description Languages

Automated Test Case Generation for Digital System Designs: A Mapping Study on VHDL, Verilog, and SystemVerilog Description Languages

A hybrid software-based self-testing methodology for embedded processor

On statistical behavior of branch coverage in testing behavioral VHDL models

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