A Novel Gate-Assisted Reverse-Read Scheme to Control Bit Coupling and Read Disturb for Multibit/Cell Operation in Deeply Scaled Split-Gate SONOS Flash EEPROM Cells

Datta, Arnab; Asnani, R.; Mahapatra, S.

doi:10.1109/led.2009.2025060

Cited by 6 publications

(2 citation statements)

References 10 publications

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“…They demonstrate their gap potential to be similar with short spacing (20 nm) and long spacing (80 nm). 19) Therefore, in ideal, a DG TANOS NVM with L g + spacing + L g = 160 nm and 20 nm in spacing should also perform similar results as above.…”

mentioning

confidence: 60%

Enhancement of Two-Bit Performance of Dual-Pi-Gate Charge Trapping Layer Flash Memory

Hung

Tsai

et al. 2012

Appl. Phys. Express

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This work demonstrates a dual-pi-gate TaN–Al2O3–Si3N4–SiO2–silicon (TANOS) flash memory with nanowires (NWs) channel. Simulation under modulated Fowler–Nordheim (MFN) tunneling indicates that the source-side tunneling oxide of the dual-gate (DG) TANOS NVM has an electric field larger than 6 MV/cm. A novel 2-bit operation of DG TANOS NVM can thus be performed by MFN programming and band-to-band tunneling-induced hot–hole injection (BTBTHHI) erasing. Additionally, the DG TANOS memory shows better program/erase characteristics and clearer distinguishability than a single-gate (SG) device under 2-bit operation. In reliability results, the DG TANOS memory shows better retention and endurance than the SG device.

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confidence: 60%

Enhancement of Two-Bit Performance of Dual-Pi-Gate Charge Trapping Layer Flash Memory

Hung

Tsai

et al. 2012

Appl. Phys. Express

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“…Although the application of gate-assisted reverse-read scheme can avoid bit-coupling issue in dual-bit flash cell [15], the V TH of bit-1 here is still measured in limited case (low V TH in 10 state; high V TH in 01 state) to define threshold operation window.…”

Section: Enhanced Endurance Characteristicsmentioning

confidence: 99%

A Highly Reliable 2-Bits/Cell Split-Gate Flash Memory Cell With a New Program-Disturbs Immune Array Configuration

Fang

Zhang

et al. 2014

IEEE Trans. Electron Devices

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A highly reliable 2-bits/cell split-gate flash memory cell in a novel program-disturbs immune array architecture is fabricated and demonstrated. Using a novel metal interconnect technique, a new virtual-ground array architecture is realized to greatly improve program disturbs as compared with conventional AND-type configuration. A fully self-aligned process with shallow trench isolation in cell array is also proposed for the first time to fabricate this word-line shared split-gate structure without any lithomisalignment issue. Moreover, the negative charge trap in select gate (SG) oxide during conventional poly-to-poly FowlerNordheim tunneling erase operation is found as an important contribution to the cycling degradation for cells with thin SG oxide, and a negative control gate bias erase scheme is then presented to enhance the endurance reliability in this paper. A 250-°C baking experiment (before and after cycling) is performed to explore this cell's data retention characteristics, proving the free of extrinsic and intrinsic defect. Erase and program characteristics are comparable with conventional splitgate cell as well.Index Terms-2-bits/cell, flash memory, Fowler-Nordheim (FN) tunneling, metal interconnect (MIC), self-aligned, source side injection (SSI), split-gate, virtual-ground.

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Device scaling considerations for sub-90-nm 2-bit/cell split-gate flash memory cell

Liu

et al. 2019

Solid-State Electronics

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A Novel Gate-Assisted Reverse-Read Scheme to Control Bit Coupling and Read Disturb for Multibit/Cell Operation in Deeply Scaled Split-Gate SONOS Flash EEPROM Cells

Cited by 6 publications

References 10 publications

Enhancement of Two-Bit Performance of Dual-Pi-Gate Charge Trapping Layer Flash Memory

Enhancement of Two-Bit Performance of Dual-Pi-Gate Charge Trapping Layer Flash Memory

A Highly Reliable 2-Bits/Cell Split-Gate Flash Memory Cell With a New Program-Disturbs Immune Array Configuration

Device scaling considerations for sub-90-nm 2-bit/cell split-gate flash memory cell

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