Nonvolatile memory (NVM) that is based on gate-all-around (GAA) and polycrystalline silicon (poly-Si) nanowires structure with silicon nanocrystals (NCs) as the storage nodes is demonstrated. The GAA poly-Si–SiO2–Si3N4–SiO2–poly-Si (SONOS) NVMs are also fabricated and compared. The GAA NCs NVMs have a 4.2 V of threshold voltage shift at 18 V for 1 ms, and are faster than the GAA SONOS NVMs do. In reliability studies, this NVM shows superior endurance after 104 program/erase (P/E) cycles, and loses only 14% of its charges lose after ten years at 85 °C.

This letter describes an asymmetric gate tunnel field-effect transistor (AG-TFET) with a gate-all-around (GAA) structure in the source and a planar structure in the drain. It has a low OFF-state current (6.55 × 10 −16 A/μm) and a high ON-state current (2.47 × 10 −5 A/μm) because the screening length λ of a GAA nanowire structure is half that of the planar structure. Simulations reveal that a subthreshold swing as low as 42 mV/decade and an ON/OFF current ratio as high as 10 10 are realized. The AG-TFET is easily fabricated as an actual device by simply changing the layout of gate in a general TFET fabrication.Index Terms-Asymmetry gate, band-to-band tunneling (BTBT), screening length (λ), tunnel field-effect transistor (TFET).

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Ultrathin channel trench junctionless poly-Si fieldeffect transistor (trench JL-FET) with a 2.4-nm channel thickness is experimentally demonstrated. Dry etching process is used to form trench structures, which define channel thickness (T CH ) and gate length (L G ). These devices (L G = 0.5 µm) show excellent performance in terms of steep subthreshold swing (100 mV/decade) and high I ON /I OFF current ratio (10 6 A/A) and practically negligible drain-induced barrier lowering (∼0 mV/V). The I ON current of the trench JL-FET can be further increased by the quantum confinement effect. Importantly, owing to its excellent device characteristics and simplicity of fabrication, the trench JL-FET has great potential for using in advanced 3-D-stacked IC applications. Index Terms-Trench junctionless field-effect transistor (trench JL-FET), nanowires (NWs), and three-dimensional (3-D).

This letter demonstrates a novel twin poly-Si thinfilm transistor (TFT) electrical erasable PROM (EEPROM) that utilizes trigate nanowires (NWs). The NW TFT EEPROM has superior gate control because its trigate structure provides a higher memory window and program/erase (P/E) efficiency over those of a single-channel one. For endurance and retention, the memory window can be maintained at 1.5 V after 10 3 P/E cycles and 25% charge loss for ten years of NW twin poly-Si EEPROM. This investigation explores its feasibility in future active matrix liquid crystal display system-on-panel and 3-D stacked Flash memory applications.Index Terms-Active matrix liquid crystal display, electrical erasable PROM (EEPROM), nanowires (NWs), poly-Si thin-film transistors (TFTs), system-on-panel, trigate, 3-D.