2022
DOI: 10.1109/jestpe.2022.3151192
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A Novel Gate-Controlled Dual Direction SCR With Enhanced Failure Current for On-Chip ESD Protection of Industry-Level Controller Area Network Bus

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Cited by 6 publications
(1 citation statement)
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“…Currently, in the structural design of ESD devices, designers often incorporate gate electrodes into SCR [1], LDMOS [2,3] devices to reduce the on-resistance of the current path. However, in the current design environment, these devices with gates do not effectively cascade circuits and lack standardized circuit models.…”
Section: Introductionmentioning
confidence: 99%
“…Currently, in the structural design of ESD devices, designers often incorporate gate electrodes into SCR [1], LDMOS [2,3] devices to reduce the on-resistance of the current path. However, in the current design environment, these devices with gates do not effectively cascade circuits and lack standardized circuit models.…”
Section: Introductionmentioning
confidence: 99%