A Novel HCI Reliability Model for RF/mmWave Applications in FDSOI Technology

Arfaoui, W.; Bossu, G.; Muhlhoff, A.; Lipp, D.; Manuwald, R.; Chen, T.; Nigam, T.; Siddabathula, M.

doi:10.1109/irps45951.2020.9129479

Cited by 8 publications

(1 citation statement)

References 6 publications

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“…Although HCI models degrading only DC FOMs can be used to evaluate some RF reliability characteristics [7], [8], extending the model for a more complete RF analysis is advantageous. In this paper, the measurement and characterization work in [3] is extended, by exploring the model card approach to model the degradation of several DC FOMs as well as the RF small-signal behavior, using selected parameters of BSIM-IMG, the industrial standard compact model for FDSOI.…”

Section: B Modeling the Degradation For Circuit-level Simulationsmentioning

confidence: 99%

RF small-signal modeling of HCI degradation in FDSOI NMOSFET using BSIM-IMG

Gonzalez

Lange

Chohan

et al. 2021

2021 IEEE International Integrated Reliability Workshop (IIRW)

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The increasing demand for reliable CMOS devices in high-frequency applications brings new challenges in the modeling of aging effects in transistors, with the need to also capture degradation of RF performance. In this paper, we explore the possibilities of using BSIM-IMG parameters to model HCI degradation under DC stress on a 22FDX™ FDSOI n-channel transistor. First, a selection of parameters is used to model HCI degradation and its impact on RF performance is analyzed. Furthermore, the "extension resistance model" within BSIM-IMG is used to broaden the model possibilities to capture RF performance degradation

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Section: B Modeling the Degradation For Circuit-level Simulationsmentioning

confidence: 99%

RF small-signal modeling of HCI degradation in FDSOI NMOSFET using BSIM-IMG

Gonzalez

Lange

Chohan

et al. 2021

2021 IEEE International Integrated Reliability Workshop (IIRW)

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Ka-band time-domain multiplexing front-end with minimum switch area utilization on 22 nm fully depleted silicon-on-insulator CMOS technology

Hietanen

Rusanen

Aikio

et al. 2021

Int. J. Microw. Wireless Technol.

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A time-domain duplexing radio frequency (RF) front-end with integrated antenna switch, power amplifier (PA), and low noise amplifier (LNA) was developed aiming for fifth-generation communication (5G) applications covering 24–28 GHz frequency range. Antenna switch utilizes pre-existing LNA input matching network together embedded with grounded shunt transistor switch to provide sufficient isolation of receive side from PA. Respectively, high impedance of off-state PA is assumed to achieve acceptable receive performance. Resulting output power is 13.6 dBm with 15 dB of peak small-signal gain at 28 GHz. Maximum average channel power was 4.8 dBm with 100 MHz 64-QAM OFDM signal within 5G adjacent channel power ratio and error vector magnitude specifications. Receive (RX) front-end achieves 5 dB noise figure at 24 GHz and 7 dB of peak gain. Performances of amplifiers degraded only by 2 dB from switch integration. The front-end dissipates 183 and 4.6 mW of power in transmit and receive mode, respectively. The simplistic design method minimizes cost both in circuit area (only 0.19 mm2) and design time making this front-end an attractive alternative in massive phased array applications using 22 nm complementary metal oxide semiconductor (CMOS) fully depleted silicon on insulator process.

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