A novel high performance enhanced-planar IGBT with P-type buried layer

Zhang, Jinping; Xia, Xiaojun; Li, Zehong; Li, Wei; Shan, Yadong; Ren, Min; Zhang, Bo; Li, Zhaoji

doi:10.1109/icccas.2013.6765244

Cited by 4 publications

(5 citation statements)

References 13 publications

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“…In order to have a good comparison with recently reported IGBT results, the V ceon -E off trade-off relationship for the DIE-PIGBT. Pro with W p = 4 µm, alternated trench-gate IGBT (AT-IGBT) in [16] and stepped doped collector (SDC-IGBT) in [6] with device thickness of 400 µm are also compared. It can be seen that the proposed device shows best performance among these structures.…”

Section: Resultsmentioning

confidence: 99%

“…Therefore, further increase of the concentration of CS layer (N cs ) is limited by the breakdown voltage (BV). To alleviate the negative impact of the N cs on BV, various improved methods were proposed for the PIGBT, such as trench shielded structures, and p-buried layer structure, etc [16][17][18]. For the trench shielded PIGBTs, the mesa width between trenches need to be narrowed to provide good shielding effect on the CS layer, leading to a large J sat for these structures.…”

Section: Introductionmentioning

confidence: 99%

“…The trade-off relationship for the DIE-PIGBT. Pro with Wp = 4 µm, AT-IGBT in[16] and SDC-IGBT in[6] are also compared.…”

mentioning

confidence: 99%

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Dual injection enhanced planar gate IGBT with self-adaptive hole path for better trade-off and higher SOA capability

Zhang¹,

Huang²,

Liu³

et al. 2022

Semicond. Sci. Technol.

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A novel dual injection enhanced planar gate IGBT with self-adaptive hole path (DIE-PIGBT) is proposed. A floating-P region is applied behind the emitter-connected deep trench in z direction and contacted with the N-type carrier stored (N-CS) layer for the proposed IGBT. Compared to the conventional trench shielded planar gate IGBT (CTS-PIGBT), the proposed device further alleviates the negative impact of the N-CS layer on the breakdown voltage (BV) and reduces both the on-state voltage drop (Vceon) and saturated collector current density (Jsat). Simulation results show that with the same device thickness of 400μm, the BV are 4625V and 4275V for the proposed and conventional device, respectively. The Vceon at 75A/cm2 is 2.51V for the proposed DIE-PIGBT, which is 1.13V lower than that of the CTS-PIGBT. Furthermore, with similar BV to the conventional one, the device thickness can be reduced to 355μm for the DIE-PIGBT. Pro. The total gate charge (QG) and miller plateau charge (QGC) for the proposed device are reduced by 61.0% and 89.9%, respectively. As a result, the proposed structure has better trade-off relationship between the Vceon and turn-off loss (Eoff). At the same Vceon of 2.51V, the Eoff for the DIE-PIGBT and DIE-PIGBT. Pro are 45.17mJ/cm2 and 41.01 mJ/cm2, which is reduced by 44.0% and 49.1% when compared to 80.61mJ/cm2 of the CTS-PIGBT, respectively. Moreover, the Jsat is reduced from 619A/cm2 for the CTS-PIGBT to 368A/cm2 for the DIE-PIGBT under the Vge of 15V. The short-circuit withstand time of the DIE-PIGBT is 1.9 times larger than that of the conventional device.

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Dual injection enhanced planar gate IGBT with self-adaptive hole path for better trade-off and higher SOA capability

Zhang¹,

Huang²,

Liu³

et al. 2022

Semicond. Sci. Technol.

Self Cite

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“…In addition, in the off-state, highly doped CSL generates a high E-field at the gate oxide and p-body/CSL junctions. This E-field accelerates avalanche breakdown, causing a decrement in BV [38,39].…”

Section: Introductionmentioning

confidence: 99%

Superjunction IGBT with split carrier storage layer

Yoon,

Shin,

Kim

et al. 2024

Semicond. Sci. Technol.

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The Insulated Gate Bipolar Transistor (IGBT) is crucial in high-voltage applications due to its characteristics like breakdown voltage (BV) and on-state voltage VCE(sat). However, its slower turn-off time, attributed to hole mobility, restricts its frequency range. Techniques such as the carrier storage layer (CSL) and super-junction (SJ) structures aim to optimize BV and VCE(sat) through hole density and field distribution. Combining CSL and SJ offers advantages, yet challenges remain regarding E-field concentration. In this work, the split CSL concept introduces a solution by optimizing BV and Eoff through effective field distribution and hole extraction acceleration respectively while maintaining VCE(sat). Split CSL, which is divided into a high doping layer and a low doping layer, reduces the burden on the gate oxide by distributing the E-field evenly when in the off-state due to the difference in doping concentration. And during turn-off, hole current is concentrated on LDL, which has relatively low resistance, thereby accelerating hole extraction. Simulation-based results showcase improvements in the proposed structure's properties. The further optimization of high doping layer (HDL) and low doping layer (LDL) concentrations enhances the structure's performance. It is clear that the split CSL structure presents potential for advancing IGBT capabilities. The application of the split CSL structure resulted in significant improvements: the turn-off time was reduced by 32.4% and the breakdown voltage increased by 32.5 V compared to conventional CSL-SJ structures. These enhancements highlight the effectiveness of the split CSL design in optimizing the IGBT’s performance attribute.

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“…One solution involves removing the silicon substrate completely or using an insulating substrate to replace the p-substrate. 14,15) The other one involves compensating the depletion by introducing additional n-type impurities to n-pillars near the drain, such as the SJ=reduced surface field (RESURF) structure [16][17][18][19][20][21][22] and the tapered n-and p-pillars layout. 23,24) In this paper, we demonstrate the dc and high-frequency characteristics of SJ-LDMOS transistors to assess the feasibility of SJ-LDMOS for RF applications.…”

Section: Introductionmentioning

confidence: 99%

High-frequency performances of superjunction laterally diffused metal–oxide–semiconductor transistors for RF power applications

Chen

Chiu

et al. 2016

Jpn. J. Appl. Phys.

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This paper presents the dc and high-frequency performances of laterally diffused metal–oxide–semiconductor (LDMOS) transistors with superjunction (SJ) structures. The SJ-LDMOS transistors were fabricated using a 0.5-µm CMOS process. By utilizing a modified SJ/RESURF layout (Type I) or a tapered SJ layout (Type II) in our devices, better high-frequency performances and higher breakdown voltages are achieved compared with conventional SJ counterpart, owing to the suppression of the substrate-assisted depletion effect and the reduction of the drain resistance. For Type I device with an optimal SJ layout dimension, the cutoff frequency and the breakdown voltage are 3.7 GHz and 68 V, respectively. For Type II device with a smallest p-pillar width near the drain, they can be enhanced further and reach to 4.9 GHz and 83 V. These experimental results suggest that the SJ-LDMOS can be used in the RF power amplifiers.

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A novel high performance enhanced-planar IGBT with P-type buried layer

Cited by 4 publications

References 13 publications

Dual injection enhanced planar gate IGBT with self-adaptive hole path for better trade-off and higher SOA capability

Dual injection enhanced planar gate IGBT with self-adaptive hole path for better trade-off and higher SOA capability

Superjunction IGBT with split carrier storage layer

High-frequency performances of superjunction laterally diffused metal–oxide–semiconductor transistors for RF power applications

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