A novel high performance carrier stored trench bipolar transistor (CSTBT) with dual shielding structure (DSS-CSTBT) is proposed in this paper. The proposed DSS-CSTBT features a double trench structure with different trench profiles in the surface, in which a shallow gate trench is shielded by a deep emitter trench and a thick oxide layer under it. Compared with the conventional CSTBT (Con-CSTBT), the proposed DSS-CSTBT not only alleviates the negative impact of the shallow gate trench and highly doped CS layer on the breakdown voltage (BV) but also well reduces the gate-collector capacitance (C
GC), gate charge (Q
G) and turn off loss (E
OFF) of the device. Furthermore, lower turn on loss (E
ON) and gate drive loss (E
DR) are also obtained. Simulation results show that with the same CS layer doping concentration (N
CS) of 1.5×1016 cm-3, the BV increases from 1312 V of the Con-CSTBT to 1423 V of the proposed DSS-CSTBT with oxide layer thickness under gate (T
og2) of 1μm. Moreover, compared with the Con-CSTBT, the C
GC at V
CE of 25 V and miller plateau charge (Q
GC) for the proposed DSS-CSTBT with T
og2 of 1μm are reduced by 79.4% and 74.3%, respectively. With the V
GE increases from 0 V to 15 V, the total Q
G for the proposed DSS-CSTBT with T
og2 of 1μm is reduced by 49.5%. As a result, at the same on-state voltage drop (V
CEON) of 1.55 V, the E
ON and E
OFF are reduced from 20.3 mJ/cm2 and 19.3 mJ/cm2 for the Con-CSTBT to 8.2 mJ/cm2 and 9.7 mJ/cm2 for the proposed DSS-CSTBT with T
og2 of 1μm, respectively. Thus, the proposed DSS-CSTBT not only significantly improves the trade-off relationship between the V
CEON and E
OFF but also greatly reduces the E
ON.