A novel high-speed 4-bit carry generator with a new structure for arithmetic operations

Ghasemzadeh, Mehdi; Mohabbatian, Neda; Akbari, Amin; Hadidi, Khayrollah; Khoei, Abdollah

doi:10.1109/mixdes.2014.6872172

Cited by 3 publications

(2 citation statements)

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“…Then, they select some variation of any one of the partial products reduction schemes, such as Wallace trees or compressor trees [6], [7], [8] in the second step to rapidly reduce the number of partial product rows to the final two (sums and carries). In the third step, they use some kind of advanced adder approach such as carry-look ahead [9], [10] or carry-select adders [7], [8] to add the final two rows, resulting in the final product. A design reported in [10] saved one stage of carry save adders by removing extra signed row with a tree type two's complementary.…”

Section: Introductionmentioning

confidence: 99%

An ultra high speed booth encoder structure for fast arithmetic operations

Ghasemzadeh

Akbari

Hadidi

2015

2015 22nd International Conference Mixed Design of Integrated Circuits &Amp; Systems (MIXDES)

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A novel high speed booth encoder is designed by utilizing a new truth table. The important advantage of this structure is its low delay with respect to the previously presented papers. Moreover, generating partial products and putting the partial products array in order are done at the same time. Simulation results applied to the Hspice software in TSMC 0.18μm technology proves that the total delay of the proposed structure is about 170ps.

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Section: Introductionmentioning

confidence: 99%

An ultra high speed booth encoder structure for fast arithmetic operations

Ghasemzadeh

Akbari

Hadidi

2015

2015 22nd International Conference Mixed Design of Integrated Circuits &Amp; Systems (MIXDES)

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“…A high performance method to lower the latency of the accumulation stage is to use carry save adders (CSA) in Wallace and Dadda trees [5]. Another method is called carry look ahead adder (CLA) which is used in many articles [6]. To lower the latency of the mentioned step, 7-2 compressors have been widely employed nowadays for high speed multipliers [7][8][9][10][11][12][13].…”

Section: Introductionmentioning

confidence: 99%

A new ultra high speed 7-2 compressor with a new structure

Ghasemzadeh

Akbari

Soltani

et al. 2015

2015 22nd International Conference Mixed Design of Integrated Circuits &Amp; Systems (MIXDES)

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This paper devotes to a new 7-2 compressor designed according to a new architecture with a pure Glitchless output. A considerable increase in the speed of the operation is achieved by utilizing a new truth table, fast production of signals C out1 and C out2 , optimum tuning of the width of the utilizing transistors, and eliminating the parasitic capacitances through merging the drain of transistors. Additionally, the number of transistors used in this architecture (74) is less than the recent 7-2 compressors. The proposed structure's delay proved by the results of the simulations applied to Hspice software using standard TSMC 0.18μm CMOS technology is about 285ps.

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