An ultra high speed booth encoder structure for fast arithmetic operations

Abstract

A novel high speed booth encoder is designed by utilizing a new truth table. The important advantage of this structure is its low delay with respect to the previously presented papers. Moreover, generating partial products and putting the partial products array in order are done at the same time. Simulation results applied to the Hspice software in TSMC 0.18μm technology proves that the total delay of the proposed structure is about 170ps.

Design and Simulation of a 2GHz, 64×64 bit Arithmetic Logic Unit in 130nm CMOS Technology

“…1 Arithmetic Logic Unit(ALU) 2 Central Processing Unit(CPU) 3 Carry Select Adder (CSA) 4 Carry Lookahead Adder (CLA) 5 Partial Product 6 Modified Booth Encoder (MBE) 7 Wallace Tree 8 Compressor 9 Counter 10 Pipeline 11 Add-on 12 Transmission gate (TG) 13 Multiplicand 14 Power Delay Product(PDP)…”