A novel high-speed and low-power negative voltage level shifter for low voltage applications

Abstract

A novel high-speed and low-power negative level shifter suitable for low voltage applications is presented. To reduce the switching delay and leakage current, a novel bootstrapping technique is designed for the level shifter. Furthermore, a pull-down driver is proposed to have high driving capability under different operation modes. The circuit has been designed in 130nm 1.5V/5V triple-well CMOS technology with a nominal power supply V DD of 1.5V and a negative voltage of -4.5V. Simulation results show that the switching delay and power consumption have been significantly reduced by roughly 62% and 65%, respectively. In addition, the proposed level shifter realizes a wide operation margin with a lower V DD compared to conventional implementations.

T/R RF Switch with 150 ns Switching Time and over 100 dBc IMD for Wideband Mobile Applications in Thick Oxide SOI Process

“…Level shifters that have been applied in this design have been shown in Figure 14a,b [27]. Figure 14a shifts the control signals from 0−VDD range to VNN−0 range where VNN is −VDD.…”

A bipolar output voltage pulse transformer boost converter with charge pump assisted shunt regulator for thermoelectric energy harvesting

“…Charge pump output voltage (V HIGH ) across secondary storage capacitor C HV at noload condition is 3 V. Recent works [13] implemented this topology using CMOS 0.18-μm process, showing 77% efficiency when converting 0.9 V to 1.7 V. Moreover, with adaptive dead-time technique proposed by [14], such charge pump topologies is shown to be compatible with supply voltage down to 0.15 V. Using negative voltage (-V DD ) instead of ground (0 V) to drive the bottom supply rail of charge pump, the output voltage level can be further increased [15]. Since the boost converter at earlier stage already generated the negative supply required, no extra auxiliary charge pump is necessary to generate negative voltage, which is usually necessary as shown in [14] [16]. The unipolar clock generated on-chip needs to be converted to bipolar voltage level.…”

“…To perform the necessary level shifting i.e. from (0V 1V) to (-1V +1V), a bootstrapping negative switch driver [16] is used in this work; where the topology is shown in Fig. 4(b).…”

Performance analysis of multi-scaling voltage level shifter for low-power applications

“…The reported circuit in study by Sven and Ulrich (2010) operates correctly across process corners for supply voltages from 100 mV to 1 V on the low-voltage conditions. Liu et al (2010) proposed a negative voltage level shifter to reduce the switching delay and direct current leakage current; a novel bootstrapping technique is used to improve the drivability of pull-up transistors. The circuit by Liu et al (2010), the pulldown driver is designed to produce higher driving capability under different conditions.…”

“…Liu et al (2010) proposed a negative voltage level shifter to reduce the switching delay and direct current leakage current; a novel bootstrapping technique is used to improve the drivability of pull-up transistors. The circuit by Liu et al (2010), the pulldown driver is designed to produce higher driving capability under different conditions. Tan and Sun (2002) introduced a level shifter circuit using bootstrapped gate drive to minimize voltage swing.…”