A Novel Low-Temperature Microcap Packaging using SU-8 Bonding

Kim, Y.K.; Yi, Seung-Hwan; Kim, S.W.; Ju, Byeong−Kwon

doi:10.1109/sensor.2007.4300581

Cited by 5 publications

(4 citation statements)

References 10 publications

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“…However, there is still a crucial issue in this method with regard to the fabrication of polymer caps forming cavities on a target device. Conventionally, it has been achieved by using a sacrificial layer [4,5], or transferring pre-fabricated packaging caps [6][7][8].…”

Section: Introductionmentioning

confidence: 99%

Low-temperature, low-loss zero level packaging techniques for RF applications by using a photopatternable dry film

Kim¹,

Seok²,

Rolland³

et al. 2012

J. Micromech. Microeng.

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This paper presents a low-temperature zero-level packaging technique using a dry film type of PerMX polymer for RF devices. Silicon cap packaging with PerMX sealing ring and PerMX cap packaging through multilayer lamination have been implemented. All of the fabrication process has been performed at temperature less than 150 • C. The influence of each packaging cap on the packaged coplanar waveguide was first investigated using the HFSS electromagnetic simulation. The RF measurement results showed that both packaging caps did not have significant influence on the performance of transmission lines. The insertion loss changes before and after packaging were almost negligible up to 30 GHz, and the return losses were better than 20 dB. Also, the deformation of PerMX structures concerning the packaging processes has been studied. For silicon capping, the volumetric compression of PerMX sealing ring by the bonding process has been observed. For PerMX cap packaging, the deflection of the polymer cap has been investigated as a function of sealing ring width for the different cap size. Measured results had good agreement with the ANSYS simulated ones.

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Section: Introductionmentioning

confidence: 99%

Low-temperature, low-loss zero level packaging techniques for RF applications by using a photopatternable dry film

Kim¹,

Seok²,

Rolland³

et al. 2012

J. Micromech. Microeng.

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“…Theses processes have the advantage to provide a localized encapsulation which can be aligned easily and accurately but they suffer from one or several of the following drawbacks: (a) the process is complex especially in the case of micro or nano electromechanical systems which must be also released after cap film deposition, (b) the process needs a large amount of processing on the device wafer and is often specific to it, (c) aggressive and/or long chemical or plasma etching are typically required to remove the sacrificial layer, (d) most published works use films deposited at high temperature like LPCVD polysilicon, LPCVD silicon nitride or PSG films (Ikeda et al 1990;Cohen et al 1996;Candler et al 2003;Lin et al 1998;Lebovitz et al 1995;Tsuchiya et al 2001;He and Kim 2005, and (e) the cap film thickness may be not sufficient to obtain a cap with a high stiffness so pillars must be added (Tsuchiya et al 2001). Another more versatile way to perform thin film encapsulation is to transfer a molded film cap from a carrier wafer to the host wafer with devices to be encapsulated (Cohen et al 1996;Jourdain et al 2003;Seok et al2006;Kim et al 2007;Brault et al 2008). Another more versatile way to perform thin film encapsulation is to transfer a molded film cap from a carrier wafer to the host wafer with devices to be encapsulated (Cohen et al 1996;Jourdain et al 2003;Seok et al 2006;He and Kim 2005;Kim et al 2007;Brault et al 2008).…”

Section: Introductionmentioning

confidence: 99%

“…Another more versatile way to perform thin film encapsulation is to transfer a molded film cap from a carrier wafer to the host wafer with devices to be encapsulated (Cohen et al 1996;Jourdain et al 2003;Seok et al2006;Kim et al 2007;Brault et al 2008). Another more versatile way to perform thin film encapsulation is to transfer a molded film cap from a carrier wafer to the host wafer with devices to be encapsulated (Cohen et al 1996;Jourdain et al 2003;Seok et al 2006;He and Kim 2005;Kim et al 2007;Brault et al 2008). We investigate in this paper an alternative thin film packaging process based on mechanical release of the film shell owing to the use of an anti-adhesion film.…”

Section: Introductionmentioning

confidence: 99%

MEMS packaging process by film transfer using an anti-adhesive layer

et al. 2010

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A low cost and low temperature thin film packaging process based on the transfer of an electroplated Nickel 3D cap is proposed. This process is based on adhesion control of a thick molded cap Ni film on the carrier wafer by using a plasma deposited fluorocarbon film, on mechanical debonding and on adhesive bonding of the microcaps on the host wafer with BCB sealing rings. Mechanical characterizations show that the transferred microcaps have a high stiffness, a low stress and a high adhesion. Because this process is simple and only involves a low temperature (250°C) heating of the host wafer, it is highly versatile and suitable for the encapsulation of micro and nano devices, circuits and systems elaborated on a large range of substrate materials.

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“…Silicon wafer bonding has been a subject of interest for many years for potential with a variety of applications. The adhesive wafer bonding technique uses an intermediate adhesive layer to create a bond between two wafer substrates (1). Adhesive wafer bonding possesses a number of advantages over other established wafer bonding techniques and provides the ability to join different type of materials.…”

Section: Introductionmentioning

confidence: 99%

Optimization of Silicon-Silicon Adhesive Wafer Bonding

2010

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Optimization of bonding parameters to develop a low temperature adhesive wafer bonding process for silicon was studied. SU-8 was used as the adhesive. The Key Process Input Variables were soft bake temperature, UV exposure and bonding temperature. The soft bake temperatures were 70 o C, 90 o C and 95 o C. UV exposure energies were 50 mJ/cm 2 , 100 mJ/cm 2 and 150 mJ/cm 2 and bonding temperatures of 90 o C, 115 o C and 140 o C were studied to optimize the curing process. The quality of the bonds was determined by two Key Process Output Variables: the fraction of interfacial area in intimate contact, measured by void area, and the strength of the bond interaction, measured by tensile strength. A general linear statistical model was used to determine the impact of the KPIVs on the KPOVs. The optimum conditions are soft bake temperature: 90 o C, UV exposure: 100 mJ/cm 2 and bonding temperature: 115 o C.

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A Novel Low-Temperature Microcap Packaging using SU-8 Bonding

Cited by 5 publications

References 10 publications

Low-temperature, low-loss zero level packaging techniques for RF applications by using a photopatternable dry film

Low-temperature, low-loss zero level packaging techniques for RF applications by using a photopatternable dry film

MEMS packaging process by film transfer using an anti-adhesive layer

Optimization of Silicon-Silicon Adhesive Wafer Bonding

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