A Novel Macro-Block Group Based AVS Coding Scheme for Many-Core Processor

Abstract

Implementation of video coding systems such as H.264/AVC and AVS on multi-core and many-core platforms is attracting much attention. The slice-level parallelism is popular in parallel video coding for its simplicity and flexibility, however, the video quality loses greatly since the partitioning of slices breaks the dependency between macro-blocks, especially on multi-core or many-core platforms. To address this problem, we propose a Macro-Block Group (MBG) parallel scheme for parallel AVS coding. In the proposed scheme, video frames are equally divided into rectangular MBG regions; each MBG consists of more rows and less columns of macro-blocks than the slice-level scheme. Given that MBG is not syntactically supported by AVS, a vertical partitioning scheme is introduced. Additionally, we use mode confining and motion vector difference adjusting techniques to keep consistent with the standard. Two MBG parallel schemes (5×9 MBG partition and 8×7 MBG partition) are developed on a TILE64 manycore platform, where P/B frames use the MBG parallel scheme and I frames use the macro-block-level parallelism. Experimental results show that the proposed scheme of 5×9 MBG partition can achieve a reduction of 52% (IPPP) and 41% (IBBP) quality loss while keeping the same speed-up compared with the slice-level parallelism. With more cores employed, the scheme of 8×7 MBG partition gains 23.9 times of speed-up compared with the single-core implementation and achieves similar coding performance as the 5×9 scheme.

H.264/AVC high definition intra coding implementation on multiprocessor system on chip technology architecture

“…Therefore each CPU executes the same program but with different sets of data elements. In fact, Wang et al [27] proposed an MB level parallelism (MBLP), where each MB is processed on distinct CPU. Takeuchi et al [28] choose an MB line level partitioning (MBLLP) where each image is composed by MBL and each MBL is performed on separate CPU.…”