2014 11th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technolo 2014
DOI: 10.1109/ecticon.2014.6839711
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A novel memory controller architecture

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“…The host processor can also select the desired memory core (FLASH or DRAM) through the memory core select signal. This universal memory controller enhances the problem of turning off the clock to reduce the clock consumed power by a clock enable signal which has a huge impact on the supported power levels as shown in Fig.2 [8].…”
Section: Introductionmentioning
confidence: 99%
“…The host processor can also select the desired memory core (FLASH or DRAM) through the memory core select signal. This universal memory controller enhances the problem of turning off the clock to reduce the clock consumed power by a clock enable signal which has a huge impact on the supported power levels as shown in Fig.2 [8].…”
Section: Introductionmentioning
confidence: 99%