Implementation and verification of a generic universal memory controller based on UVM

Abstract

Abstract‫ـــــ‬ This paper presents a coverage driven constraint random based functional verification method based on the Universal Verification Methodology (UVM) using System Verilog for generic universal memory controller architecture. This universal memory controller is looking forward to improving the performance of the existing memory controllers through a complete integration of the existing memory controllers features in addition of providing novel features. It also reduces the consumed power through providing high power consumption control due to its proposed different power levels supported to fit all power scenarios. While implementing a worthy architecture like the proposed generic universal memory controller, UVM is the best choice to build well-constructed, high controlled and reusable verification environment to efficiently verify it. More than 200 coverage points have been covered to verify the validation of the integrated features which makes the proposed universal memory controller replaces the existing controllers on the scene as it provides all of their powerful features in addition of novel features to control two of the most dominated types of memory; FLASH and DRAM through one memory controller.

An expert system for checking the correctness of memory systems using simulation and metamorphic testing

“…Then, they used bounded model checking, a technique for checking the satisfiability of a property. Khalifa and Salah presented a generic universal memory controller Khalifa & Salah (2015). This approach is based on a system-level architecture that has been verified using the universal verification methodology.…”

“…Although there are numerous advantages related to the use of model checking for analysing the correctness of systems, like the high coverage it achieves, the previously described ap-proaches entail different issues, which are alleviated by our proposed system. First, these solutions are focused on verifying memory controllers with an ad-hoc model design and, therefore, these require specific requirements for each design, like a reference TLM model Khalifa & Salah (2015) and a specific register-transfer level implementation Kayed et al (2014). Hence, in order to successfully achieve a new version of the scheduler, several temporal logic constraints must be re-adapted and re-written for each memory controller.…”