A Novel Methodology for Evaluating the Energy Consumption of IP Blocks in System-Level Designs

Knödtel, Johannes; Schwabe, Wolffhardt; Lieske, Tobias; Reichenbach, Marc; Fey, Dietmar

doi:10.1109/patmos.2018.8464149

Cited by 2 publications

(1 citation statement)

References 8 publications

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“…The proposed simulation-based Transpilation method in [16], translates the gate-level component from Verilog to C, trains an energy model while providing an executable script to run system simulation and subsequently calculates energy consumption. This method is fast compared to co-simulation and test-benches approaches but it is partially valid since it does not take into consideration glitches effects and static energy.…”

Section: White/black-box Ipsmentioning

confidence: 99%

High-level power estimation techniques in embedded systems hardware: an overview

et al. 2022

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Power optimization has become a major concern for most digital hardware designers, particularly in early design phases and especially in limited power budget systems (battery-operated hand-held devices, electro-optical pluggable modules, IoT and green energy systems, etc.). Subsequently, early power consumption estimation at design time is crucial for power optimization. The aim of this paper is to present an overview of High-Level power estimation techniques currently available along with a comprehensive comparison between different methodologies and their applications on estimated models. When high speed and high performance are key features of a specific embedded system, increase in energy consumption becomes the main hurdle to be tackled while keeping speed/performance v/s power consumption trade-off at a minimum. This paper provides designers, interested in power consumption modeling, with knowledge on how to select best power estimation techniques applied to designated target models.

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Section: White/black-box Ipsmentioning

confidence: 99%

High-level power estimation techniques in embedded systems hardware: an overview

et al. 2022

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Transpilers: A Systematic Mapping Review of Their Usage in Research and Industry

2023

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Transpilers refer to a special type of compilation that takes source code and translates it into target source code. This type of technique has been used for different types of implementations in scientific studies. A review of the research areas related to the use of transpilers allows the understanding of the direction in this branch of knowledge. The objective was to carry out an exhaustive and extended mapping of the usage and implementation of transpilers in research studies in the last 10 years. A systematic mapping review was carried out for answering the 5 research questions proposed. The PSALSAR method is used as a guide to the steps needed for the review. In total, from 1181 articles collected, 683 primary studies were selected, reviewed, and analyzed. Proposals from the industry were also analyzed. A new method for automatic data tabulation has been proposed for the mapping objective, using a relational database and SQL language. It was identified that the most common uses of transpilers are related to performance optimizations, parallel programming, embedded systems, compilers, testing, AI, graphics, and software development. In conclusion, it was possible to determine the extent and identification of research sub-areas and their impact on the usage of the transpilers. Future research could be considered about the usage of transpilers in transactional software, migration strategies for legacy systems, AI, math, multiplatform games and apps, automatic source code generation, and networking.

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A Novel Methodology for Evaluating the Energy Consumption of IP Blocks in System-Level Designs

Cited by 2 publications

References 8 publications

High-level power estimation techniques in embedded systems hardware: an overview

High-level power estimation techniques in embedded systems hardware: an overview

Transpilers: A Systematic Mapping Review of Their Usage in Research and Industry

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