A novel methodology for speeding up IC performance in 32nm FinFET

Abstract

This paper presents a novel methodology for IC speed-up in 32 nm FinFET. By taking advantage of independently controlling two gates of IG-FinFET, we develop the boosting structures that can improve the signal propagation on interconnect significantly. Furthermore, the circuit area and power dissipation issues are also taken into account. With the addition of boosting path, the full booster can reduce the delay of interconnect as much as 50% while consuming merely more than 18% of power. In the high-speed and low-power IC designs, the proposed boosting structure gives circuit designers several options in the trade-off between the power consumption and high performance which play an important role in application-specific integration circuits in the 22 nm node and beyond.

Modeling symmetrical independent gate FinFET using predictive technology model

“…As a result, circuit area and parasitic capacitance would decrease in static and dynamic circuits. Using back-gate voltage, the front-gate threshold voltage can be controlled, accordingly leakage current reduces [23] and speed increases in interconnection [24]. In this section different schemes of circuit design using IGFinFETs and different NAND gates are explained.…”