In this paper, we simulated the dependence of the effect of reducing the drain-induced barrier lowering on the thickness of a buried oxide layer in a finned (vertical) metal-oxide-semiconductor field effect transistor (FinFET) based on silicon-on-insulator technology. Three shapes of the fin with the rectangle, trapezoid, and triangle cross sections were considered. The drain-induced barrier lowering effect significantly depends on both the fin shape and the thickness of the buried oxide layer. The smallest drain-induced barrier lowering effect occurs when the thickness of the buried oxide layer is small for the fin of a triangular shape. This behavior of the drain-induced barrier lowering effect is strongly correlated with the behavior of the parasitic capacitance between a gate and a source.