A Novel Net Weighting Algorithm for Power and Timing-Driven Placement

Abstract

Nowadays, many new low power ASICs applications have emerged. This new market trend made the designer’s task of meeting the timing and routability requirements within the power budget more challenging. One of the major sources of power consumption in modern integrated circuits (ICs) is the Interconnect. In this paper, we present a novel Power and Timing-Driven global Placement (PTDP) algorithm. Its principle is to wrap a commercial timing-driven placer with a nets weighting mechanism to calculate the nets weights based on their timing and power consumption. The new calculated weight is used to drive the placement engine to place the cells connected by the critical power or timing nets close to each other and hence reduce the parasitic capacitances of the interconnects and, by consequence, improve the timing and power consumption of the design. This approach not only improves the design power consumption but facilitates also the routability with only a minor impact on the timing closure of a few designs. The experiments carried on 40 industrial designs of different nodes, sizes, and complexities and demonstrate that the proposed algorithm is able to achieve significant improvements on Quality of Results (QoR) compared with a commercial timing driven placement flow. We effectively reduce the interconnect power by an average of 11.5% that leads to a total power improvement of 5.4%, a timing improvement of 9.4%, 13.7%, and of 3.2% in Worst Negative Slack (WNS), Total Negative Slack (TNS), and total wirelength reduction, respectively.

Comprehensive Review of Optimal Utilization of Clock and Power Resources in Multi Bit Flip Flop Techniques

“…During physical synthesis, authors have tried and succeeded in developing the physical design flow for MBFFs. The developed works are divided into three different categories: 1) MBFFs pre-placement optimization (25) , 2) In-placement register banks optimization (26) , 3) MBFFs post-placement optimization (27) .…”

“…Instead of following the heuristic criteria to generate register banks in large size and disassembling the banks for incremental placement in recent works (30) , it's better to adopt different problem formulation in the post-placement stage to generate MBFFs with the satisfaction of placement and timing constraints. N/A The total minimum power of the flip-flop (25) Maximum rout ability The total minimum power of the flip-flop [27] Minimum total wire length The total minimum power of the flip-flop and wire length (27) Minimum total net switching power Net switching power and total minimum number of clock sinks (28) Minimum total wire length Total minimum flip-flop power…”

Machine Learning Application for Output Capacitance Accuracy Improvement: A Case Study for Combinational Cells

“…However, during logic optimization of the technology-mapped Netlist, the Synthesis tools define the timing paths and estimate delays through each path. An accurate timing analysis engine at this preliminary stage will significantly impact subsequent steps of design flow . Various ASIC development and EDA companies urge improving the accuracy of the Quality of Result (QoR) metrics in the early design stages.…”

“…An accurate timing analysis engine at this preliminary stage will significantly impact subsequent steps of design flow. 1 Various ASIC development and EDA companies urge improving the accuracy of the Quality of Result (QoR) metrics in the early design stages. Thus, precise cell and net delays at preplacement reduce the iterative process of ASIC design, which directly impacts the time-to-market factor.…”