A novel Network-on-Chip security algorithm for tolerating Byzantine faults

Abstract

Since the number of processors and cores on a single chip is increasing, the interconnection among them becomes significant. Network-on-Chip (NoC) has direct access to all resources and information within a System-on-Chip (SoC), rendering it appealing to attackers. Malicious attacks targeting NoC are a major cause of performance depletion and they can cause arbitrary behavior of links or routers, that is, Byzantine faults. Byzantine faults have been thoroughly investigated in the context of Distributed systems however not in Very Large Scale Integration (VLSI) systems. Hence, in this paper we propose a novel fault model followed by the design and implementation of lightweight algorithms, based on Software Defined Network-on-Chip (SDNoC) architecture. The proposed algorithms can be used to build highly available NoCs and can tolerate Byzantine faults. Additionally, a set of different scenarios has been simulated and the results demonstrate that by using the proposed algorithms the packet loss decreases between 65% and 76% under Transpose traffic, 67% and 77% under BitReverse and 55% and 66% under Uniform traffic.

Wireless Network-on-Chip Security Review: Attack Taxonomy, Implications, and Countermeasures

“…Due to the latency and overhead, many solutions opt for a lightweight countermeasure. For example, arbitrary failure like the Byzantine fault is addressed in [24], where these faults are caused by HTs or DoS attacks, targeting the network's availability. A lightweight handshake mechanism with ACKs and ALERT messages is implemented to ensure the delivery of packets and detect malicious nodes, respectively.…”

“…In this case, it monitors the number of Request-to-Send signals using temporal duration to classify the attack. However, this method's accuracy depends on the duration of the attack in the temporal sample, as accuracy increases from 60% to 87% when the attack duration progresses from 30% Lightweight handshake authentication [24] Increased latency by a factor of 10-40%.…”

A Survey of MPSoC Management toward Self-Awareness

“…System reliability is affected by the faults that the system may incur, so many researchers have designed architectures and management schemes to anticipate and avoid certain types of failures. The types of failures identified within systems-on-chip, especially in new MPSoCs, fall into three main categories: transient, permanent, and intermittent faults [149]. These failures are caused by effects such as soft (cosmic) errors, crosstalk, electromagnetic interference (EMI), intersymbol interfer-ence, noise, electromigration, and aging of materials [150,151].…”

“…Transient faults have a random behavior occurring in one or several execution cycles, while permanent are due to wholly damaged components that cause logic faults or operation delays. Intermittent faults have repetitive behavior and occur in the same place [149]. Several MPSoCs include spare structures to tolerate some of these failures, leveraging the increased number of processing elements.…”