A Novel p-LDMOS Additionally Conducting Electrons by Control ICs

Guo, Song; Chen, Xing Bi

doi:10.1109/jeds.2019.2930630

Cited by 2 publications

(2 citation statements)

References 16 publications

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“…Lateral diffused metal-oxide-semiconductor field-effect transistor (LDMOS) devices have been efficiently applied to ICs for power electronics, power managements and display driver, given their advantages of low ON-resistance and ability to withstand high operating voltages [10][11][12][13][14][15][16]. Therefore, design methods for each operating voltage devices to develop various HV and low-voltage devices by using single-process chips are crucial for many applications.…”

Section: Introductionmentioning

confidence: 99%

Layout Strengthening the ESD Performance for High-Voltage N-Channel Lateral Diffused MOSFETs

et al. 2020

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An electrostatic discharge (ESD) event can negatively affect the reliability of integrated circuits. Therefore, improving on ESD immunity in high-voltage (HV) n-channel (n) lateral diffused metal–oxide–semiconductor field-effect transistor (HV nLDMOS) components through drain-side layout engineering was studied. This involved adjusting the operating voltage, improving the non-uniform turned-on phenomenon, and examining the effects of embedded-device structures on ESD. All proposed architectures for improving ESD immunity in this work were measured and evaluated using a transmission-line pulse system. The corresponding trigger voltage (Vt1), holding voltage (Vh) and secondary breakdown current (It2) results of the tested devices were obtained. This paper first addresses the drift-region length modulation to design different operating voltages, which decreased as the drift region length and shallow trench isolation (STI) length shrunk. When an HV nLDMOS device decreased to the shortest drift region length, the Vt1 and Vh values were closest to 21.85, and 9.27 V, respectively. The It2 value of a low-voltage operated device could be increased to a maximum value of 3.25 A. For the channel width modulation, increasing the layout finger number of an HV LDMOS device did not really help the ESD immunity that because it may suffer the problem of non-uniform turned-on phenomenon. Therefore, adjusting the optimized channel width was the best one method of improvement. Furthermore, to improve the low ESD reliability problem of nLDMOS devices, two structures were used to improve the ESD capability. The first was a drain side—embedded silicon-controlled rectifier (SCR). Here, the SCR PNP-arranged type in the drain side had the best ESD capability because the SCR path was short and had been prior to triggering; however, it also has a latch-up risk and low Vh characteristic. By removing the entire heavily doped drain-side N+ region, the equivalent series resistance in the drain region was increased, so that the It2 performance could be increased from 2.29 A to 3.98 A in the structure of a fully embedded drain-side Schottky diode. This component still has sufficiently high Vh behaviour. Therefore, embedding a full Schottky-diode into an HV nLDMOS in the drain side was the best method and was efficient for improving the ESD/Latch-up abilities of the device. The figure of merit (FOM) of ESD, Latch-up, and cell area considerations improved to approximately 80.86%.

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Section: Introductionmentioning

confidence: 99%

Layout Strengthening the ESD Performance for High-Voltage N-Channel Lateral Diffused MOSFETs

et al. 2020

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“…In recent years, the UHV LDMOS has been implemented in power electronics, Microelectromechanical systems (MEMS) domains, power management circuits, and internet of things (IoT) applications [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16]. The power management circuit is also an indispensable project of the internet of things.…”

Section: Introductionmentioning

confidence: 99%

Electrostatic-Discharge-Immunity Impacts in 300 V nLDMOS by Comprehensive Drift-Region Engineering

2019

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Electrostatic discharge (ESD) events are the main factors impacting the reliability of Integrated circuits (ICs); therefore, the ESD immunity level of these ICs is an important index. This paper focuses on comprehensive drift-region engineering for ultra-high-voltage (UHV) circular n-channel lateral diffusion metal-oxide-semiconductor transistor (nLDMOS) devices used to investigate impacts on ESD ability. Under the condition of fixed layout area, there are four kinds of modulation in the drift region. First, by floating a polysilicon stripe above the drift region, the breakdown voltage and secondary breakdown current of this modulation can be increased. Second, adjusting the width of the field-oxide layer in the drift region when the width of the field-oxide layer is 5.8 μm will result in the minimum breakdown voltage (105 V) but the best secondary breakdown current (6.84 A). Third, by adjusting the discrete unit cell and its spacing, the corresponding improved trigger voltage, holding voltage, and secondary breakdown current can be obtained. According to the experimental results, the holding voltage of all devices under test (DUTs) is greater than that of the reference group, so the discrete HV N-Well (HVNW) layer can effectively improve its latch-up immunity. Finally, by embedding different P-Well lengths, the findings suggest that when the embedded P-Well length is 9 μm, it will have the highest ESD ability and latch-up immunity.

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A Novel p-LDMOS Additionally Conducting Electrons by Control ICs

Cited by 2 publications

References 16 publications

Layout Strengthening the ESD Performance for High-Voltage N-Channel Lateral Diffused MOSFETs

Layout Strengthening the ESD Performance for High-Voltage N-Channel Lateral Diffused MOSFETs

Electrostatic-Discharge-Immunity Impacts in 300 V nLDMOS by Comprehensive Drift-Region Engineering

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