High-voltage n-channel lateral-diffused metal-oxide-semiconductor field-effect transistor (nLDMOS) components, fabricated by a TSMC 0.25-μm 60-V bipolar-CMOS-DMOS (BCD) process with drain-side embedded silicon-controlled rectifier (SCR) of the n-p-n-arranged and p-n-p-arranged types, were investigated, in order to determine the devices’ electrostatic discharge (ESD)-sensing behavior and capability by discrete anode engineering. As for the drain-side n-p-n-arranged type with discrete-anode manners, transmission–line–pulse (TLP) testing results showed that the ESD ability (It2 value) was slightly upgraded. When the discrete physical parameter was 91 rows, the optimal It2 reached 2.157 A (increasing 17.7% compared with the reference sample). On the other hand, the drain-side SCR p-n-p-arranged type with discrete-anode manner had excellent SCR behavior, and its It2 values could be increased to >7 A (increasing >281.9% compared with the reference DUT). Moreover, under discrete anode engineering, the drain-side SCR n-p-n-arranged and p-n-p-arranged types had clearly higher ESD ability, except for the few discrete physical parameters. Therefore, using the anode discrete engineering, the ESD dissipation ability of a high-voltage (HV) nLDMOS with drain-side SCRs will have greater effectiveness.

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In general, the antielectrostatic discharge (ESD) ability of a high voltage (HV) MOSFET device will be very low if it is not optimized through the addition of reliability engineering. Accordingly, in this paper, some embedded superjunction (SJ) device under tests (DUTs) of 45-V HV n-channel lateral-diffused MOS (nLDMOS) are developed, which offer a low on-resistance as compared with the traditional nLDMOS due to the redistribution of electric field or/and higher doping density in the drain side. In order to evaluate how various physical parameters affect the anti-ESD capability, these DUTs will change the widths and shapes of the P/N pillars. From the testing results, it can be found that the I t2 values of SJ-nLDMOS DUTs will be higher than that of a traditional nLDMOS, while the equivalent immunity level is even greater than HBM 10 kV. In this paper, the I t2 values of developed SJ-nLDMOS DUTs were increased at least by 109%, 31%, and 159% over that of the traditional nLDMOS for the Types 1-3 embedded SJ, respectively. Moreover, in some geometry architectures of an SJ-LDMOS, the holding voltage can be greater than the traditional nLDMOS. Therefore, by considering the relationships between these three kinds of SJ-nLDMOS DUTs and the I t2 values, it can be determined that the SJ structure is good for ESD/latch-up immunities especially for the ESD reliability. Index Terms-Bipolar-CMOS-DMOS(BCD), electrostatic discharge (ESD), high voltage (HV), latch-up, low voltage, n-channel lateral-diffused MOS (nLDMOS), secondary breakdown current (I t2 ), superjunction (SJ), transmission-line pulse (TLP).

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