A Novel Parametrized Fused Division and Square-Root POSIT Arithmetic Architecture

Raveendran, Aneesh; Jean, Sandra; Mervin, J; Vivian, D; Selvakumar, David

doi:10.1109/vlsid49098.2020.00053

Cited by 12 publications

(15 citation statements)

References 6 publications

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“…In addition, the area cost of the dividers without QDS table in [10] and [22] are similar to the proposed divider. However, the proposed divider in this paper adopts the method of division with non-restoring remainder, so that the error of partial remainder caused by the error of estimation quotient digits can be corrected in the next iteration, the error accumulation will be eliminated automatically.…”

Section: Results and Comparisonmentioning

confidence: 58%

“…The structure of QDS table in [10] is similar to [7]. The function of QDS table is realized by using multi-stage comparators, and better performance can be obtained in the design of low-radix divider.…”

Section: Results and Comparisonmentioning

confidence: 99%

“…However, an additional period is required to detect and correct the partial quotient digits after each iteration cycle. It can be seen from Table 4 that compared with the structure in [10] and [29], the period of the divider in [22] needs to be doubled under the same radix and calculation precision. However, compared with the structure in [29], the area cost of the divider without the QDS table will be significantly reduced.…”

Section: Results and Comparisonmentioning

confidence: 99%

“…Compared with the structure in [10], the proposed estimation algorithm of the partial quotient digits has better expansibility and can be extended to a higher performance divider with any radix. Although the data of [10] shows that it is similar to the proposed divider in terms of area cost, the maximum operating frequency of the raidx-4 divider is the same as the proposed divider with radix-16 in this paper. Therefore, the proposed architecture of divider can achieve higher circuit performance in the high-radix design.…”

Section: Results and Comparisonmentioning

confidence: 99%

“…The estimation calculation process generates partial remainder U i as shown in (10). Note that U 0 = P in this case.…”

Section: B Proposed Algorithmmentioning

confidence: 99%

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An Architecture of Area-Effective High Radix Floating-Point Divider With Low-Power Consumption

2021

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In this paper, a novel architecture of area-effective high-radix floating-point divider with low power consumption is proposed. By extending the principle of the standard SRT algorithm, the divider can estimate the partial quotient digits by a simpler circuit and tolerate certain calculation errors in each recurrence cycle. In addition, the accumulation of errors in the recurrence process can be eliminated automatically without additional calculation cycle. The latency and area cost of the divider are linear with the radix number, which solves the problem that the quotient digits selection tables in high-radix divider have high area cost. Base on the proposed architecture a single-precision floating-point divider is implemented, which has an area of 6037.20um 2 in 65nm process. The dynamic power consumption of the divider is only 0.848mW at 250MHz. Compared with other dividers reported in the literature, the area cost can be reduced by about 90% with the same computation precision and performance.INDEX TERMS High-radix, division, SRT, quotient-digits-selection.

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Section: Results and Comparisonmentioning

confidence: 58%

Section: Results and Comparisonmentioning

confidence: 99%