A Novel ReRAM-based Main Memory Structure for Optimizing Access Latency and Reliability

Zhang, Yang; Feng, Dan; Liu, Jingning; Tong, Wei; Wu, Bing; Fang, Caihua

doi:10.1145/3061639.3062191

Cited by 17 publications

(10 citation statements)

References 6 publications

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“…In addition, the unselected wordlines and bitlines are set to a certain voltage to avoid disturbing other cells in the array. A Half-Wordline Half-Bitline (HWHB) write scheme is widely adopted for the crossbar array [59,60,67]. With HWHB, when a RESET operation is performed, the selected bitline is applied with a full voltage V wr ite, the selected wordline is grounded, and all of the unselected wordlines and bitlines are half biased at V wr ite /2.…”

Section: Reram Array Structurementioning

confidence: 99%

“…However, in previous works, the write disturbance is not discussed or excessively considered. In these researches [54,60,65,67], the write disturbance in ReRAM arrays results in suboptimal reliability. On the other hand, in Ghofrani et al [11], the RESET disturbance and SET disturbance are equally treated.…”

Section: Motivationmentioning

confidence: 99%

“…1-DFS contains three phases: read, analysis, and write. The algorithm of 1-DFS scheme is similar to our previous work [67]. 1) Read phase: 1-DFS leverages a read-before-write scheme to reduce the N i .…”

Section: -Dominated Flip Schemementioning

confidence: 99%

“…Otherwise, the new data will be directly written into the crossbar array with a flip flag bit "1". The algorithm of the 0-DFS scheme is similar to our previous work [67].…”

Section: -Dominated Flip Schemementioning

confidence: 99%

“…As ITRS indicates, the scaling path of DRAM beyond 16nm is not clear [57]. Consequently, emerging Nonvolatile Memories (NVMs) such as Phase Change Memory (PCM), Spin-Transfer Torque RAM (STT-RAM), and Resistive RAM (ReRAM) are actively explored as replacements for DRAM due to their better scalability with low power consumption and high density [25,27,44,54,65,67,70]. Among these candidates, ReRAM is the most promising due to its lower power consumption and higher density.…”

Section: Introductionmentioning

confidence: 99%

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Feng

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et al. 2018

ACM Trans. Archit. Code Optim.

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Emerging Resistive Random Access Memory (ReRAM) is a promising candidate as the replacement for DRAM due to its low standby power, high density, high scalability, and nonvolatility. By employing the unique crossbar structure, ReRAM can be constructed with extremely high density. However, the crossbar ReRAM faces some serious challenges in terms of performance, reliability, and energy consumption. First, ReRAM's crossbar structure causes an IR drop problem due to wire resistance and sneak currents, which results in nonuniform access latency in ReRAM banks and reduces its reliability. Second, without access transistors in the crossbar structure, write disturbance results in serious data reliability problem. Third, the access latency, reliability, and energy use of ReRAM arrays are significantly influenced by the data patterns involved in a write operation. To overcome the challenges of the crossbar ReRAM, we propose a novel circuit architecture co-optimization framework for improving the performance, reliability, and energy use of ReRAM-based main memory system, called CACF. The proposed CACF consists of three levels, including the circuit level, circuit architecture level, and architecture level. At the circuit level, to reduce the IR drops along bitlines, we propose a double-sided write driver design by applying write drivers along both sides of bitlines and selectively activating the write drivers. At the circuit architecture level, to address the write disturbance with low overheads, we propose a RESET disturbance detection scheme by adding disturbance reference cells and conditionally performing refresh operations. At the architecture level, a region partition with address remapping method is proposed to leverage the nonuniform access latency in ReRAM banks, and two flip schemes are proposed in different regions to optimize the data patterns involved in a write operation. The experimental results show that CACF improves system performance by 26.1%, decreases memory access latency by 22.4%, shortens running time by 20.1%, and reduces energy consumption by 21.6% on average over an aggressive baseline. Meanwhile, CACF significantly improves the reliability of ReRAM-based memory systems.

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Section: Reram Array Structurementioning

confidence: 99%

Section: Motivationmentioning

confidence: 99%

Section: -Dominated Flip Schemementioning

confidence: 99%

“…Otherwise, the new data will be directly written into the crossbar array with a flip flag bit "1". The algorithm of the 0-DFS scheme is similar to our previous work [67].…”

Section: -Dominated Flip Schemementioning

confidence: 99%