A Novel Resistive Switching Identification Method through Relaxation Characteristics for Sneak-path-constrained Selectorless RRAM application

Chen, Ying‐Chen; Lin, Chia‐Hua; Hu, Szu-Tung; Lin, Chih-Yang; Fowler, Burt; Lee, John

doi:10.1038/s41598-019-48932-5

Cited by 39 publications

(27 citation statements)

References 37 publications

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“…Although there have been many proposals for monolithic 3D-integration of neuromorphic chips, an integration of 3D-IC with eNVMs for neuromorphic applications is still missing. Among a many eNVMs resistive random-access RRAMs are one of the most promising candidates for neural network applications [16][17][18][19][20][21]. In this article we propose and demonstrate by simulation -IGZO based novel 3Dembedded RRAM tile with common WL and SL for neuromorphic computing (Fig.…”

Section: Introductionmentioning

confidence: 99%

Ferroelectric FET analog synapse for acceleration of deep neural network training

Jerry

Chen

Zhang

et al. 2017

2017 IEEE International Electron Devices Meeting (IEDM)

460

371

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In this paper we propose and evaluate the performance of a 3D-embedded neuromorphic computation block based on indium gallium zinc oxide ( -IGZO) based nanosheet transistor and bi-layer resistive memory devices. We have fabricated bi-layer resistive random-access memory (RRAM) devices with Ta2O5 and Al2O3 layers. The device has been characterized and modeled. The compact models of RRAM and -IGZO based embedded nanosheet structures have been used to evaluate the system level performance of 8 vertically stacked -IGZO based nanosheet layers with RRAM for neuromorphic applications. The model considers the design space with uniform bit line (BL), select line (SL) and word line (WL) resistance. Finally, we have simulated the weighted sum operation with our proposed 8-layer stacked nanosheet based embedded memory and evaluated the performance for VGG-16 convolutional neural network (CNN) for Fashion-MNIST and CIFAR-10 data recognition, which yielded 92% and 75% accuracy respectively with drop out layers amid device variation.

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Section: Introductionmentioning

confidence: 99%

Ferroelectric FET analog synapse for acceleration of deep neural network training

Jerry

Chen

Zhang

et al. 2017

2017 IEEE International Electron Devices Meeting (IEDM)

460

371

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“…Various methods have been suggested to eliminate or mitigate the sneak paths problem 10 . As per the recent research article “Research progress on solutions to the sneak path issue in memristor crossbar arrays” by Shi et al, 11 the existing techniques to address the sneak path problem are 1D1M (1 diode and 1 memristor), 1T1M, (1 transistor and 1 memristor), and 1S1M (1 diode and 1 selector).…”

Section: Memristor Based Memorymentioning

confidence: 99%

“…Research work published by Chen et al 10 indicates that the resistive random access memory is one of the leading memory in the competition of next‐generation nonvolatile memory technologies. Despite excellent characteristics of resistive memories, one of the potential obstacles for the production of memories is the sneak paths causing intervention between neighboring memory cells and hence may conclude in misinterpretation of stored values.…”

Section: Introductionmentioning

confidence: 99%

Memristor‐based 2D1M architecture: Solution to sneak paths in multilevel memory

Ravi

Singh

Reka

2020

Trans Emerging Tel Tech

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The memristor, the fourth fundamental elements have shown the potential to revolutionize the present storage, analog, and digital computational technologies. The ability to remember its previous state in the absence of any stimuli has made the memristor as a prime candidate for nonvolatile memory. However, the sneak path is one of the main problems hampering the implementation of memristor‐based crossbar memories. In this article, we introduce a new crossbar architecture that is capable of storing multibit per cell and eliminates the sneak paths without adding any complex circuitry. The approximate write delay of the proposed memory cell is 20 mS which is very close to the delay of the single bit cell. The proposed architecture was validated by storing four different logic states in each cell of the 4 × 4 memory. Hence, one memory cell of the proposed architecture replaces four cells of the single‐bit memory at the cost of one additional diode per cell. Therefore, the proposed scheme saves considerable area when compared with the conventional single‐bit memory array. The write/read operations are validated by a generic, accurate, and efficient “voltage threshold adaptive memristor” (VTEAM) model. The simulation results prove that the proposed circuitry can read the memory content even after 2000 cycles without any sneak paths problem.

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“…Therefore, a device with both functions of a memory cell and a nonlinear access element is required in order to solve the problem. In this regard, several solutions have been tried to solve this problem, which include 1 diode and 1 resistor (1D-1R) [15], 1 transistor and 1 resistor (1T-1R) [16], and 1 selector and 1 resistor (1S-1R) [17].…”

Section: Introductionmentioning

confidence: 99%

Self-Rectifying Characteristics Observed in O-Doped ZrN Resistive Switching Memory Devices Using Schottky Barrier Type Bottom Electrode

Jung

Lee²,

Kim

et al. 2021

IEEE Access

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In this study, we investigated the self-rectifying characteristics of p-Si/O-doped ZrN/TiN structures in order to overcome a disturbance between neighboring cells in array structures. The proposed device shows a nonlinear selection characteristic and a Schottky diode property in the positive bias region.We also observed the rectifying region within -2 V, which suppresses the interference with neighboring cells that occurs during a reading operation. Any RS phenomena is not observed especially for the reverse bias sweep to reset the proposed device, which indicated that the proposed device has an intrinsic rectifying property. The proposed device shows the highest current ratio of 6×10 2 at -4.5 V and a maximum current limiting capability in the bias region above -2 V. In addition, the O-doped ZrN memory device shows a stable retention up to 10 4 seconds at 125 °C as well as a high read margin of 380. Therefore, the proposed device suppresses interference in the read operation without additional selector elements, enabling stable memory operation.

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A Novel Resistive Switching Identification Method through Relaxation Characteristics for Sneak-path-constrained Selectorless RRAM application

Cited by 39 publications

References 37 publications

Ferroelectric FET analog synapse for acceleration of deep neural network training

Ferroelectric FET analog synapse for acceleration of deep neural network training

Memristor‐based 2D1M architecture: Solution to sneak paths in multilevel memory

Self-Rectifying Characteristics Observed in O-Doped ZrN Resistive Switching Memory Devices Using Schottky Barrier Type Bottom Electrode

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