Memristor‐based 2D1M architecture: Solution to sneak paths in multilevel memory

Abstract

The memristor, the fourth fundamental elements have shown the potential to revolutionize the present storage, analog, and digital computational technologies. The ability to remember its previous state in the absence of any stimuli has made the memristor as a prime candidate for nonvolatile memory. However, the sneak path is one of the main problems hampering the implementation of memristor‐based crossbar memories. In this article, we introduce a new crossbar architecture that is capable of storing multibit per cell and eliminates the sneak paths without adding any complex circuitry. The approximate write delay of the proposed memory cell is 20 mS which is very close to the delay of the single bit cell. The proposed architecture was validated by storing four different logic states in each cell of the 4 × 4 memory. Hence, one memory cell of the proposed architecture replaces four cells of the single‐bit memory at the cost of one additional diode per cell. Therefore, the proposed scheme saves considerable area when compared with the conventional single‐bit memory array. The write/read operations are validated by a generic, accurate, and efficient “voltage threshold adaptive memristor” (VTEAM) model. The simulation results prove that the proposed circuitry can read the memory content even after 2000 cycles without any sneak paths problem.

Insulator Metal Transition-Based Selector in Crossbar Memory Arrays

“…Another approach is developing advanced READ/WRITE algorithms that accommodate sneak path currents [15,16]. Despite these mitigation strategies, managing sneak path currents remains a complex challenge that requires careful consideration in the design and operation of crossbar memory arrays [17].…”

“…On the other hand, there is the 1S1R architecture, in which each memory cell consists of a resistive switching element in series with a selector device, as shown in Figure 5b. The selector is, in this case, a non-linear device, often realized using diodes [18], ovonic Another approach is developing advanced READ/WRITE algorithms that accommodate sneak path currents [15,16]. Despite these mitigation strategies, managing sneak path currents remains a complex challenge that requires careful consideration in the design and operation of crossbar memory arrays [17].…”

Recent Progress in Selector and Self‐Rectifying Devices for Resistive Random‐Access Memory Application

“…For instance, selector devices should have a very small OFF current, high ON current, excellent switching speeds, and maximum cyclic endurance. [ 87 ] In addition, the operating voltage of the selector device and fabrication process should be compatible with memory devices. Different types of selector devices have been reported in the literature.…”

A multi-value 3D crossbar array nonvolatile memory based on pure memristors

“…To solve this problem, switches are required in the cell structure to prevent the current flow through the unexpected cells. Early researchers proposed a memory cell structure of one diode and one memristor (1D1R) [34], then a more common one transistor and one memristor structure (1T1R) [35], recently, a 2D1M memory cell is proposed [38]. But the use of diode and transistor changes the memory cell circuits to a hybrid circuit, which decreases the storage density.…”