A Novel Reversible Zs Gate and Its Application for Optimization of Quantum Adder Circuits

Abstract

The key of optimizing quantum reversible logic lies in automatically constructing quantum reversible logic circuits with the minimal quantum cost. This paper constructs a 4 × 4 reversible gate called ZS gate to build quantum full adder. At the same time, a novel reversible No-Wait-Carry adder (or carry skip adder) by using ZSCGPD based on ZS gate with the least cost is also designed. The adder circuit using the proposed ZSCGPD is much better and optimized than other researchers' counterparts both in terms of garbage outputs, number and kind of reversible gates, and quantum cost. In order to show the efficiency of the proposed designs, lower bounds of the reversible carry skip adder in terms of garbage outputs and quantum cost are proposed as well.

Toward Designing High-Speed Cost-Efficient Quantum Reversible Carry Select Adders

“…bits Proposed RCA Square Root CSLA Adder [25] Adder [21] Adder [23] Adder [22] Adder 1 [28] Adder 2 [28] Adder [ square root method, as it results in minimum possible delay and a reasonable quantum cost for the addition operation.…”

“…In 2011, Haghparast et al represented an n-bits adder structure using the ripple carry method utilizing HNG gates, which results in a total quantum cost and delay of 6n [21]. Zhou et al proposed a reversible adder structure based on the carry look-ahead method [22] to optimize the reversible adder circuit in propagation delay, but their design could not bring about superior results in terms of delay and quantum cost compared to reversible ripple carry circuits. He indicated that although some architectures like the carry look-ahead adders in conventional digital designing methodology provide less propagation delay than the ripple carry method, reversible and quantum designs might contradict these standard rules due to their different optimization objective and designing principles of conventional logic designs.…”

“…* n number of bits of the adder, S: size of the smallest block, L: size of the largest block, K: total number of blocks Adder [25] Adder [21] Adder [23] Adder [22] Adder 1 [28] Adder 2 [28] Adder [33] CSLA (here) Where the term written in the form of sigma summation calculates the total quantum cost of all QBEC modules, and the rest of the formula computes the total quantum cost of RCA circuits and multiplexer modules. This calculation has been formalized based on the overall size of the adder structure (n), size of the smallest block (S), the total size of all blocks except smallest one (n-S), and the number of stages (K).…”

Novel Synthesis Methodology for Fault Tolerant Reversible Circuits by Bounded Model Checking for Linear Temporal Logic

“…LTL cannot assert the existence of paths. We express the complement property of formula (9) in formula (10).…”

Performance Analysis of Reversible Finite Field Arithmetic Architectures Over GF(p) and GF(2m) in Elliptic Curve Cryptography

“…8,12 Many algorithms were proposed in literature to perform reversible logic synthesis and optimize their performance metrics. 13,14 Two new reversible logic gates known as TSG gate 15 and ZS gate 16 were proposed to design quantum circuits. In addition, di®erent structures of reversible adders 17,18 and reversible multipliers 19,20 were proposed to design reversible arithmetic and logic unit (ALU).…”