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The key of optimizing quantum reversible logic lies in automatically constructing quantum reversible logic circuits with the minimal quantum cost. This paper constructs a 4 × 4 reversible gate called ZS gate to build quantum full adder. At the same time, a novel reversible No-Wait-Carry adder (or carry skip adder) by using ZSCGPD based on ZS gate with the least cost is also designed. The adder circuit using the proposed ZSCGPD is much better and optimized than other researchers' counterparts both in terms of garbage outputs, number and kind of reversible gates, and quantum cost. In order to show the efficiency of the proposed designs, lower bounds of the reversible carry skip adder in terms of garbage outputs and quantum cost are proposed as well.

Quantum computer requires quantum arithmetic. The sophisticated design of a reversible arithmetic logic unit (reversible ALU) for quantum arithmetic has been College