Optimization Approaches for Designing a Novel 4-Bit Reversible Comparator

Evolution of Structure of Some Binary Group-Based N-Bit Compartor, N-To-2N Decoder by Reversible Technique

“…Individual cell performance parameters analyze for reducing input voltage and finding power consumption, delay etc. [4] Y N N Available Circuit [3] N N Y Available Circuit [12] N N N Available Circuit [13] N N N Available Circuit [15] N N N Available Circuit [6] Y N N Available Circuit [5] Y…”

“…In 2013, Ri-gui Zhou et.al. [5] It's performing all logical operation NAND, NOR, AND, OR, HA, HS, FA and FS and also form efficient groupbased n-bit reversible comparator and n-to-2 n bit decoder with low value of reversible parameters.…”

Design Approaches for a Novel Reversible 4-bit Comparator

“…Also, the ancillary inputs used are 6 in number with a delay of 3 units and 3 garbage outputs. The author used a NLG gate whose quantum cost is justified to be 2 [6], due to which the total quantum cost of the single bit comparator circuit becomes 26.…”

“…Every input must reach to at least one output. For Reversible logic to be achieved, some conditions must prevail [6].…”

“…Quantum Computing is that branch of computing in which the computational elementary operations are done by using sub-atomic data carriers [6]. For example, electron spinning in either directions anticlockwise and clockwise, may be justified as basis binary |1〉 or |0〉, the ket notation.…”