Novel Design for Reversible Arithmetic Logic Unit

Zhou, Ri-Gui; Li, Yancheng; Zhang, Manqun; Hu, Bin

doi:10.1007/s10773-014-2255-x

Cited by 4 publications

(3 citation statements)

References 19 publications

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“…This region presents the refined structure of a reversible n-bit ALU reliant on a controlled quantum full adder proposed by Kai-Wen Cheng et al with a progressive strategy of tasks [16]. The proposed reversible ALU hopes complete the accompanying fundamental game plan of assignments,…”

Section: Alumentioning

confidence: 99%

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Secure Fault Diagnosis for Framework on Chip Design and Testing

Swapna*,

Kamalahasan,

Mishra

et al. 2020

IJITEE

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Because of the extensive expense of semiconductor fabricating, most framework on-chip structure organizations redistribute their generation to seaward foundries. As a large portion of these gadgets are fabricated in situations of constrained trust that regularly need suitable oversight, various diverse dangers have risen. These incorporate unapproved overabundance of the ICs, offer of out-of-determination/rejected ICs disposed of by assembling tests, robbery of scholarly property, and figuring out of the structures. The Boolean calculations are effectively break keybased confusion techniques and therefore go around the essential destinations of metering and confusion. In this research paper, we present an innovation secure cell plan for executing the structure for-security foundation to avoid releasing the way to a foe under any conditions and produce fault free integrated circuit design. Our proposed structure is impervious to different known assaults at the expense of a next to no region overhead. This Proposed Framework Actualized utilizing Verilog HDL also recreated by Modelsim 6.4 c and Integrated by Xilinx device.

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Section: Alumentioning

confidence: 99%

mentioning

confidence: 99%

Secure Fault Diagnosis for Framework on Chip Design and Testing

Swapna*,

Kamalahasan,

Mishra

et al. 2020

IJITEE

View full text Add to dashboard Cite

show abstract

“…The proposed circuit performs limited operations yet quantum cost is too high. Authors proposed ALU with high functionality and proposed ALU can be used for reversible programmable logic device [12].…”

Section: Introductionmentioning

confidence: 99%

High functionality reversible arithmetic logic unit

Thakral

Bansal

2020

IJECE

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Energy loss is a big challenge in digital logic design primarily due to impending end of Moore’s Law. Increase in power dissipation not only affects portability but also overall life span of a device. Many applications cannot afford this loss. Therefore, future computing will rely on reversible logic for implementation of power efficient and compact circuits. Arithmetic and logic unit (ALU) is a fundamental component of all processors and designing it with reversible logic is tedious. The various ALU designs using reversible logic gates exist in literature but operations performed by them are limited. The main aim of this paper is to propose a new design of reversible ALU and enhance number of operations in it. This paper critically analyzes proposed ALU with existing designs and demonstrates increase in functionality with 56% reduction in gates, 17 % reduction in garbage lines, 92 % reduction in ancillary lines and 53 % reduction in quantum cost. The proposed ALU design is coded in Verilog HDL, synthesized and simulated using EDA (Electronic Design Automation) tool-Xilinx ISE design suit 14.2. RCViewer+ tool has been used to validate quantum cost of proposed design.

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2020

Reversible and DNA Computing

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Novel Design for Reversible Arithmetic Logic Unit

Abstract: Quantum computer requires quantum arithmetic. The sophisticated design of a reversible arithmetic logic unit (reversible ALU) for quantum arithmetic has been College

Cited by 4 publications

References 19 publications

Secure Fault Diagnosis for Framework on Chip Design and Testing

Secure Fault Diagnosis for Framework on Chip Design and Testing

High functionality reversible arithmetic logic unit

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