Novel designs for fault tolerant reversible binary coded decimal adders

Zhou, Ri-Gui; Li, Yan-Cheng; Zhang, Manqun

doi:10.1080/00207217.2013.832388

Cited by 28 publications

(18 citation statements)

References 10 publications

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“…In [29] a more efficient BCD adder is proposed with a considerable reduction in the garbage outputs and quantum cost where they are reduced to 14 and 84, respectively. Besides, a more recent work [28] could reduce the quantum cost of this type of fault-tolerant adder to 61 by incorporating three new parity preserving gates but increased the number of garbage outputs to 18. Moreover, a CSK-based BCD adder is proposed in [28] with the quantum cost of 81.…”

Section: Fault-tolerant Reversible Adder Architecturesmentioning

confidence: 98%

“…So far, many parity preserving reversible adder architectures have been proposed that among them ripple carry adders [10,12,27,28] are simply constructed by using the parity preserving reversible full adders described before, with the quantum cost that linearly increases with the adder size. However, the first parity preserving BCD adder [8] which uses a carry skip adder, as well, is a one-digit BCD adder with the quantum cost of 148.…”

Section: Fault-tolerant Reversible Adder Architecturesmentioning

confidence: 99%

“…In [10] after introducing a new gate, MIG, a full adder is constructed by using two MIGs with the quantum cost of 14. However, both full adder designs presented in [27,28] benefits from a new 5 × 5 gate that after setting their two last inputs to zero, operate as a parity preserving full adder but with the quantum cost of 14 and 8, respectively. It is worth mentioning that the introduced parity preserving full adders also differ in the other criterions that will be investigated later.…”

Section: Fault-tolerant Reversible Full Addersmentioning

confidence: 99%

“…The full adder presented in [12] requires three F2Gs and a NFT gate with the total quantum cost of 11. The designs proposed in [10,27,28] use a new gate to achieve a parity preserving full adder. In [10] after introducing a new gate, MIG, a full adder is constructed by using two MIGs with the quantum cost of 14.…”

Section: Fault-tolerant Reversible Full Addersmentioning

confidence: 99%

“…Here, we introduce a new 5 × 5 reversible gate called low-complexity gate (LCG) that has a very low hardware complexity compared to previous similar gates proposed in [9,10,12,[26][27][28] as well as a small quantum cost. This gate is used to construct a new low-cost parity preserving full adder.…”

Section: New Low-cost Reversible Gatementioning

confidence: 99%

See 4 more Smart Citations

Novel low-cost and fault-tolerant reversible logic adders

Valinataj

Mirshekar

Jazayeri

2016

Computers & Electrical Engineering

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Section: Fault-tolerant Reversible Adder Architecturesmentioning

confidence: 98%

Section: Fault-tolerant Reversible Adder Architecturesmentioning

confidence: 99%

Section: Fault-tolerant Reversible Full Addersmentioning

confidence: 99%

Section: Fault-tolerant Reversible Full Addersmentioning

confidence: 99%

Section: New Low-cost Reversible Gatementioning

confidence: 99%

See 3 more Smart Citations

Novel low-cost and fault-tolerant reversible logic adders

Valinataj

Mirshekar

Jazayeri

2016

Computers & Electrical Engineering

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A new design of parity preserving reversible Vedic multiplier targeting emerging quantum circuits

Noorallahzadeh

Mosleh

Ahmadpour

et al. 2023

Int J Numerical Modelling

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Reversible logic is used increasingly to design digital circuits with lower power consumption. The parity preserving (PP) property contributes to detect permanent and transient faults in reversible circuits by comparing the input and output parity. Multiplication is also considered one of the primary operations in both digital and analog circuits due to its wide applications in digital signal processing and computer arithmetic operations. Accordingly, Vedic mathematics, as a set of techniques sutras, has become popular and is extensively used to solve mathematical problems more efficiently and faster. This work proposes three PP reversible blocks, N1, N2, and N3, which are used to develop a novel effective 2‐bit PP reversible Vedic multiplier and 4‐bit ripples carry adders (RCAs). Moreover, 2‐bit Vedic multiplier and RCA are used to develop the 4‐bit PP reversible Vedic multiplier. The proposed designs outperform the most relevant state‐of‐the‐art structures in terms of garbage output (GO), constant input (CI), gate count (GC), and quantum cost (QC). Average savings of 22.37%, 35.44%, 35.44%, and 34.76%, and 17.76%, 26.60%, 24.52%, and 27.27% respectively, are observed for two‐bit and four‐bit PP reversible Vedic multipliers in terms of QC, GO, CI and GC as compared to previous works.

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