2014 International Test Conference 2014
DOI: 10.1109/test.2014.7035303
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A novel RF self test for a combo SoC on digital ATE with multi-site applications

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Cited by 10 publications
(7 citation statements)
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“…A number of works can be found in the literature, e.g. based on the use of a reference transceiver accompanied by a FPGA to handle the interface between the transceiver and a digital ATE [1], or based on the use of a processor embedded in a radio SoC to implement self-test and provide low-frequency digital output [2], or defining a digital ATE system with multi-level drivers and comparators for direct modulation/demodulation of QAM signals [3]. More recently, a solution based on direct 1-bit under-sampled acquisition has been proposed that permits the test of ZigBee transmitters on a standard digital ATE [4,5].…”
Section: Introductionmentioning
confidence: 99%
“…A number of works can be found in the literature, e.g. based on the use of a reference transceiver accompanied by a FPGA to handle the interface between the transceiver and a digital ATE [1], or based on the use of a processor embedded in a radio SoC to implement self-test and provide low-frequency digital output [2], or defining a digital ATE system with multi-level drivers and comparators for direct modulation/demodulation of QAM signals [3]. More recently, a solution based on direct 1-bit under-sampled acquisition has been proposed that permits the test of ZigBee transmitters on a standard digital ATE [4,5].…”
Section: Introductionmentioning
confidence: 99%
“…In [3], a solution based on an additional reference transceiver and an FPGA at board level was proposed to interface with the digital domain of the ATE. In [4], a dedicated self-test processor is embedded into the SoC under test to provide low-frequency digital output. An off-chip direct modulation / demodulation scheme was proposed in [5].…”
Section: Introductionmentioning
confidence: 99%
“…In [2], a reference transceiver is used to handle test signal generation/reception, accompanied by a FPGA that interfaces the reference transceiver with the digital ATE. In [3], the digital processor embedded in a radio SoC is used to implement a self-test so that only low-speed digital signals have to be processed by the digital ATE. In [4], a digital ATE system is developed for RF devices with QAM single interfaces based on the concept of direct modulation/demodulation with multilevel drivers and comparators.…”
Section: Introductionmentioning
confidence: 99%