A Novel Self-Reference Technique for STT-RAM Read and Write Reliability Enhancement

Zhang, Yaojun; Wen, Wujie; Joshi, Rajiv V.; Li, Hai; Chen, Yiran

doi:10.1109/tmag.2014.2323196

Cited by 19 publications

(9 citation statements)

References 8 publications

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“…Where, 𝑉 𝐵𝐿−𝐿𝑜𝑤 and 𝑉 𝐵𝐿−𝐻 𝑖𝑔ℎ are the bit line voltages when the MTJ is at low and high resistance states, respectively. In these equations, 𝑅 𝐿 and 𝑅 𝐻 are the low and high MTJ resistance, respectively, 𝑅 𝑁 𝑀 𝑂𝑆 is the resistance of NMOS access transistor, and 𝐼 𝑟 𝑒𝑎𝑑 is read current [38], [39]. By applying 𝐼 𝑟 𝑒𝑎𝑑 to an STT-MRAM cell, a voltage is generated between the bit line and source line.…”

Section: B Read and Write Operationsmentioning

confidence: 99%

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A System-Level Framework for Analytical and Empirical Reliability Exploration of STT-MRAM Caches

2020

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𝑆 𝑝𝑖𝑛-𝑇𝑟𝑎𝑛𝑠 𝑓 𝑒𝑟 𝑇 𝑜𝑟𝑞𝑢𝑒 𝑀𝑎𝑔𝑛𝑒𝑡𝑖𝑐 𝑅 𝐴𝑀 (STT-MRAM) is known as the most promising replacement for SRAM technology in large 𝐿𝑎𝑠𝑡-𝐿𝑒𝑣𝑒𝑙 𝐶𝑎𝑐ℎ𝑒 memories (LLCs). Despite its high-density, non-volatility, near-zero leakage power, and immunity to radiation as the major advantages, STT-MRAMbased cache memory suffers from high error rates mainly due to 𝑟𝑒𝑡𝑒𝑛𝑡𝑖𝑜𝑛 𝑓 𝑎𝑖𝑙𝑢𝑟𝑒, 𝑟𝑒𝑎𝑑 𝑑𝑖𝑠𝑡𝑢𝑟𝑏𝑎𝑛𝑐𝑒, and 𝑤𝑟𝑖𝑡𝑒 𝑓 𝑎𝑖𝑙𝑢𝑟𝑒. Existing studies are limited to estimate the rate of 𝑜𝑛𝑙 𝑦 one or two of these error types for STT-MRAM cache. However, the overall vulnerability of STT-MRAM caches, which its estimation is a must to design cost-efficient reliable caches, has not been offered in none of previous studies.In this paper, we propose a system-level framework for reliability exploration and characterization of errors behavior in STT-MRAM caches. To this end, we formulate the cache vulnerability considering the inter-correlation of the error types including retention failure, read disturbance, and write failure as well as the dependency of error rates to workloads behavior and 𝑃𝑟𝑜𝑐𝑒𝑠𝑠 𝑉 𝑎𝑟𝑖𝑎𝑡𝑖𝑜𝑛𝑠 (PVs). Our analysis reveals that STT-MRAM cache vulnerability is highly workload-dependent and varies by orders of magnitude in different cache access patterns. Our analytical study also shows that this vulnerability divergence significantly increases by process variations in STT-MRAM cells. To take the effects of system workloads and PVs into account, we implement the error types in gem5 full-system simulator. The experimental results using a comprehensive set of multi-programmed workloads from SPEC CPU2006 benchmark suite on a quad-core processor show that the total error rate in a shared STT-MRAM LLC varies by 32.0x for different workloads. A further 6.5x vulnerability variation is observed when considering PVs in the STT-MRAM cells. In addition, the contribution of each error type in total LLC vulnerability highly varies in different cache access patterns and moreover, error rates are differently affected by PVs. The proposed analytical and empirical studies can significantly help system architects for efficient utilization of error mitigation techniques and designing highly reliable and low-cost STT-MRAM LLCs.

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Section: B Read and Write Operationsmentioning

confidence: 99%

“…The MTJ switching time depends on various parameters, e.g., MTJ switching current, process variations, thermal fluctuations, and switching pulse width. The occurrence probability of a write failure for a STT-MRAM cell is according to (6) [5], [37], [38].…”

Section: Stt-mram Reliabilitymentioning

confidence: 99%

A System-Level Framework for Analytical and Empirical Reliability Exploration of STT-MRAM Caches

2020

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“…To write '0' in the cell, the spin-polarized current flows from bit line to source line and causes the electron charges to flow from the reference layer to the free layer. Electrons with the spin direction same as that of electrons spin in the reference layer pass through the free layer and generate a torque that parallelize the two MTJ ferromagnetic layers and leads to write '0' [37], [38].…”

Section: Read and Write Operationsmentioning

confidence: 99%

TA-LRW: A Replacement Policy for Error Rate Reduction in STT-MRAM Caches

Cheshmikhani

Farbeh

Miremadi

et al. 2019

IEEE Trans. Comput.

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As technology process node scales down, on-chip SRAM caches lose their efficiency because of their low scalability, high leakage power, and increasing rate of soft errors. Among emerging memory technologies, Spin-T ransf er T orque M agnetic RAM (STT-MRAM) is known as the most promising replacement for SRAM-based cache memories. The main advantages of STT-MRAM are its non-volatility, near-zero leakage power, higher density, soft-error immunity, and higher scalability. Despite these advantages, high error rate in STT-MRAM cells due to retention f ailure, write f ailure, and read disturbance threatens the reliability of cache memories built upon STT-MRAM technology. The error rate is significantly increased in higher temperature, which further affects the reliability of STT-MRAM-based cache memories. The major source of heat generation and temperature increase in STT-MRAM cache memories is write operations, which are managed by cache replacement policy. To the best of our knowledge, none of previous studies have attempted to mitigate heat generation and high temperature of STT-MRAM cache memories using replacement policy. In this paper, we first analyze the cache behavior in conventional Least-Recently U sed (LRU) replacement policy and demonstrate that the majority of consecutive write operations (more than 66%) are committed to adjacent cache blocks. These adjacent write operations cause accumulated heat and increased temperature, which significantly increase the cache error rate. To eliminate heat accumulation and the adjacency of consecutive writes, we propose a cache replacement policy, named T hermal-Aware Least-Recently W ritten (TA-LRW), to smoothly distribute the generated heat by conducting consecutive write operations in distant cache blocks. TA-LRW guarantees the distance of at least three blocks for each two consecutive write operations in an 8-way associative cache. This distant write scheme reduces the temperature-induced error rate by 94.8%, on average, compared with the conventional LRU policy, which results in 6.9x reduction in cache error rate. The implementation cost and complexity of TA-LRW is as low as F irst-In, F irst-Out (FIFO) policy while providing a near-LRU performance, having the advantages of both replacement policies. The significantly reduced error rate is achieved by imposing only 2.3% performance overhead compared with the LRU policy.

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“…The retention time of STT-RAM cell design utilized in LRSC architecture needs to be considered properly to meet the following key design issues: 1) data stability during read operation: The data retention time should be sufficient to retain the stability of data while cache lines are accessed during read operations, otherwise the unstable data is sensed via sense amplifier, which in turn may cause the corrupted data to be provided to the CPU. Even though the sensing resolution and reliability of sense amplifiers employed in STT-RAM cache designs influence the accuracy of the sensed data [26] [27], other characteristics such as resiliency to process variation [28], performance and power consumption [29], also play paramount roles for determining the preferred sense amplifier candidate.…”

Section: Refresh Scheme For Lrscmentioning

confidence: 99%

Read-Tuned STT-RAM and eDRAM Cache Hierarchies for Throughput and Energy Optimization

Khoshavi

DeMara

2018

IEEE Access

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As capacity and complexity of on-chip cache memory hierarchy increases, the service cost to the critical loads from Last Level Cache (LLC), which are frequently repeated, has become a major concern. The processor may stall for a considerable interval while waiting to access the data stored in the cache blocks in LLC, if there are no independent instructions to execute. To provide accelerated service to the critical loads requests from LLC, this work concentrates on leveraging the additional capacity offered by replacing SRAM-based L2 with Spin-Transfer Torque Random Access Memory (STT-RAM) to accommodate frequently accessed cache blocks in exclusive read mode in favor of reducing the overall read service time. Our proposed technique partitions L2 cache into two STT-RAM arrangements with different write performance and data retention time. The retentionrelaxed STT-RAM arrays are utilized to effectively deal with the regular L2 cache requests while the high retention STT-RAM arrays in L2 are selected for maintaining repeatedly read accessed cache blocks from LLC by incurring negligible energy consumption for data retention. Our experimental results show that the proposed technique can reduce the mean L2 read miss ratio by 51.4% and increase the IPC by 11.7% on average across PARSEC benchmark suite while significantly decreasing the total L2 energy consumption compared to conventional SRAMbased L2 design.

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A Novel Self-Reference Technique for STT-RAM Read and Write Reliability Enhancement

Cited by 19 publications

References 8 publications

A System-Level Framework for Analytical and Empirical Reliability Exploration of STT-MRAM Caches

A System-Level Framework for Analytical and Empirical Reliability Exploration of STT-MRAM Caches

TA-LRW: A Replacement Policy for Error Rate Reduction in STT-MRAM Caches

Read-Tuned STT-RAM and eDRAM Cache Hierarchies for Throughput and Energy Optimization

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