A Novel SRAM Cell Design for Low Power Applications

Abstract

In this paper, we initially discuss some of the SRAM designs available like 6T SRAM and 9T SRAM and go on to propose a new 9T SRAM based cell design which proves to be more efficient in terms of power consumption and average delay. We further extend the concept and propose a 10T SRAM cell and discuss the merits and demerits of such a design. The entire paper is written focusing mainly on low power implementation of SRAM.

A Comparative Study of SRAM Cells

“…A variation of the above circuit is discussed in [5]. In this circuit, instead of the NMOS pass transistor used to cut off a path to GND, a PMOS pass transistor is used to cut off the supply form VDD when not required.…”

“…VIII. 10T SRAM Figure 7 shows a 10T SRAM cell as mentioned in [5]. This is a combination of designs in figure 4 and figure 5.…”