In this paper, we initially discuss some of the SRAM designs available like 6T SRAM and 9T SRAM and go on to propose a new 9T SRAM based cell design which proves to be more efficient in terms of power consumption and average delay. We further extend the concept and propose a 10T SRAM cell and discuss the merits and demerits of such a design. The entire paper is written focusing mainly on low power implementation of SRAM.

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Power reduction in VLSI designs is one of the key design constraints along with others, namely timing, area, quality constraints, noise, etc. Even though there has been a steady growth of devices that are able to be placed in a given area of a chip as per Moore's law, the same cannot be said for battery technologies as they have never been able to catch up. Since the advent of the deep sub-micron era, speed and higher frequency of operation have become the prime goals of any design as the hunger for faster and better optimized systems are never ending. But as a consequence of faster operating speeds which basically means higher clock frequencies, power becomes one of the main constraints to be considered as the most important component of power dissipation, namely the dynamic power dissipation has a proportional relationship with the clock frequency. Hence clock power optimization is taken up as the prime objective of this paper for technologies below 14 nm as at these technologies, other secondary power dissipation components start to become more prominent. Various design techniques have been discussed and applied at both the circuit design and the RTL levels of abstraction in order to provide a complete review of most of the low power design techniques which can be used to reduce power at both these levels of abstraction. An improvement of 25% and 15.7% of power reduction are observed in clock power and overall power respectively. There is also a power reduction of 2-5% for each of the RTL level optimization techniques. General TermsClock power optimization, Moore's law, Deep sub-micron era, Levels of abstraction.

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While the UVM-constrained random and coverage-driven verification methodology revolutionized IP and unit-level testing, it falls short of SoC-level verification needs. A solution must extend from UVM and enable vertical (IP to SoC) and horizontal (verification engine portability) reuse to completely handle SoC-level verification. To expedite test-case generation and use rapid verification engines, it must also provide a method to collect, distribute, and automatically amplify use cases. Opting a Python-based Design Verification approach opens the door to various such merits. Cocotb is a very useful, growing methodology which can be used for the same. This paper elaborates on the application of cocotb, an open-source framework hosted on Github which is based on CO-routine and CO-simulation of Testbench environment for verifying VHDL/Verilog RTL using Python. It employs equivalent design-reuse and functional verification concepts like UVM, however is implemented in Python, which is much simpler to understand and that leads to faster development and reduces the turnaround time.