A Novel Sub-5-nm Node Dual-Workfunction Folded Cascode Nanosheet FETs for Low Power Mobile Applications

Abstract

A novel sub-5-nm node folded cascode structure using dual workfunction (WF) scheme was proposed using fully-calibrated TCAD. Feasible process flows of the cascode device were adopted from those of nanosheet FETs (NSFETs) and complementary FETs. Key process flows were depositing two different separate spacers and etching one spacer selectively, depositing oxide layer in between source/drain epitaxial growths for electrical isolation, and fill-CMP-etch back sequence for dual-WF. The folded cascode device consists of two or three FETs in series, designated as 2-CAS or 3-CAS respectively, under the same active area. Conventional three-stacked NSFETs have larger transconductance (G m) than 2-CAS and 3-CAS, but the cascode devices have much larger output resistance (R o) by dual-WF scheme and thus achieve larger intrinsic gain (A V = G m R o). Smaller G m and larger gate capacitance for the cascode devices decrease the cutoff frequency. But smaller gate-to-drain capacitance by shrunk drain epi along with large R o increases the maximum frequency (F max). Especially, 2-CAS has larger A V and F max than conventional NSFETs for all the NS widths of 20, 30, and 40 nm and at all the operation voltages of 0.6, 0.7, and 0.8 V, promising for low power mobile applications.

Monolithic 3D 6T-SRAM Based on Newly Designed Gate and Source/Drain Bottom Contact Schemes

“…When the device is connected directly, the cell area and length of the bypassing metal are reduced, thus reducing the interconnect RC and improving power, performance, and area (PPA) is expected. Some previous studies [8][9][10] are already applied similar S/D direct contact schemes, but research on the advantages of M3D has not been conducted yet.…”