Performance analysis of metal gate engineered junctionless nanosheet fet with a ft/fmax of 224/342ghz for beyond 5g (b5g) applications

Valasa, Sresta; Tayal, Shubham; Thoutam, Laxman Raju

doi:10.1016/j.micrna.2023.207582

Cited by 10 publications

(6 citation statements)

References 40 publications

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“…Since the density gradient model cannot precisely capture the quantum confinement effects at ultrascaled nano dimensions, we have activated MLDA model in the TCAD simulator. 33…”

Section: Device Setup and Simulation Detailsmentioning

confidence: 99%

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Pushing the Boundaries: Design and Simulation Approach of Negative Capacitance Nanosheet FETs with Ferroelectric and Dielectric Spacers at the Sub-3 nm Technology Node for Analog/RF/Mixed Signal Applications

Valasa,

Kotha,

Vadthiya

2024

ACS Appl. Electron. Mater.

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This manuscript for the first time introduces an approach of incorporating ferroelectric (FE) spacers in the negative capacitance (NC) nanosheet (NS) field-effect transistor (FET) instead of dielectric (DE) spacers in the source/drain extension region, specifically targeting sub-3 nm technology nodes. Four configurations are proposed for the examination: Both DE, Both FE, Drain-FE Source-DE, and Source-FE Drain-DE that address the need for improved performance and proper spacer material selection. The analysis starting from device level (digital/analog/radio frequency) to circuit (CMOS inverter) as a whole package is investigated through well-calibrated TCAD simulation, and the results portrayed Source-FE Drain-DE spacer placement as the best configuration in all aspects. Through digital performance evaluation, it has been found that the I on/I off ratio improves by an amount of ∼54.96%, ∼ 39.01%, and ∼37.61% for Both FE, Drain-FE Source-DE, and Source-FE Drain-DE spacers, respectively, as compared to Both DE spacers. An insight into eradication of negative differential resistance (NDR) and reduction of the subthreshold slope is also presented through proper placement of spacer material. All the analog/RF figure of merits (FOMs) such as g m, A V, f T, f max, , gfp, tfp, and gtfp are enhanced for the Source-FE Drain-DE configuration by an amount of ∼13.4%, ∼24%, ∼70.38%, ∼41.05%, ∼43.21%, ∼ 60.89%, and ∼60.47%, respectively, as compared to the Both DE configuration. We also assessed a design space window to achieve favorable capacitance matching, aiming for the NC effect in the pursuit of an optimized device design. Moreover, the CMOS inverter (layout is also designed) and CS amplifier circuits for all the four proposed configurations are examined and it is found that Source-FE Drain-DE gives better inverter performance with a reduced delay and PDP of ∼4.38 ps and ∼26.7 aJ as compared with other configurations. Overall, this work contributes to the scientific understanding of NC-NSFETs and spacer engineering, highlighting the potential of FE materials in advancing semiconductor technologies and paving the way for future innovations in digital, analog/RF, and mixed signal applications.

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“…Since the density gradient model cannot precisely capture the quantum confinement effects at ultrascaled nano dimensions, we have activated MLDA model in the TCAD simulator. 33…”

Section: Device Setup and Simulation Detailsmentioning

confidence: 99%

“…The field effect mobility model is also employed as ultrathin dimensional layers are present in the designed NC-NSFET device. Since the density gradient model cannot precisely capture the quantum confinement effects at ultrascaled nano dimensions, we have activated MLDA model in the TCAD simulator …”

Section: Device Setup and Simulation Detailsmentioning

confidence: 99%

Pushing the Boundaries: Design and Simulation Approach of Negative Capacitance Nanosheet FETs with Ferroelectric and Dielectric Spacers at the Sub-3 nm Technology Node for Analog/RF/Mixed Signal Applications

Valasa,

Kotha,

Vadthiya

2024

ACS Appl. Electron. Mater.

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“…The absence of a junction reduces the leakage current, enhances the on/off current ratio, and enables better control of the channel doping profile. 17 These factors contribute to increased device performance, energy efficiency, and overall transistor functionality.…”

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confidence: 99%

Optimization of Sidewall Spacer Engineering at Sub-5 nm Technology Node For JL-Nanowire FET: Digital/Analog/RF/Circuit Perspective

Anguru,

Aryasomayajula,

Kotha

et al. 2024

ECS J. Solid State Sci. Technol.

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This paper presents a performance analysis of 3-stack JL-NWFETs with different spacer materials and spacer lengths. The DC and analog/RF performance is analysed at the device level, and circuit level. In single-k spacer analysis, TiO2 exhibits lowest IOFF of ~89.28%, and largest ION/IOFF ratio with better subthreshold performance of ~42.51% as compared to Air spacer at Lext= 7nm. In addition, TiO2 spacer is suitable for analog applications while Air spacer for RF applications. The dual-k spacer analysis is also performed and the TiO2+Air spacer showed prodigious DC/Analog/RF performances dominating all other combinations. Further investigations into inner high-k spacer analysis (Lsp,hk) revealed that higher Lsp,hk is suitable for DC and Analog applications whereas lower Lsp,hk for RF applications. The CS amplifier designed for configurations of Lsp,hk showed better gain for higher Lsp,hk with the amplification gain of ~4.8V/V. Overall, this analysis serves as a beacon, guiding the future of JL-NWFET design for spellbinding nano-electronic devices at sub-5nm technology node.

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“…12 An alternative way to tackle this challenge is the formation of a junctionless (JL) device wherein the device is doped uniformly averting the formation of junctions. 13 This makes the fabrication of the device easier by eliminating some steps (simplified S/D engineering) and ensures lower thermal budget and gives the flexibility to choose materials for gate electrode and gate oxide and hence regarded to be an excellent alternative to conventional FETs. 14 Furthermore, the JLFETs are immune to SCE and surface scattering amidst the interface of gate oxide and channel, and moreover exhibit high junction breakdown owing to the absence of junctions.…”

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confidence: 99%

Optimizing U-Shape FinFETs for Sub-5nm Technology: Performance Analysis and Device-to-Circuit Evaluation in Digital and Analog/Radio Frequency Applications

Ramakrishna,

Valasa,

Bhukya

et al. 2023

ECS J. Solid State Sci. Technol.

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FinFET is considered a potential contender in the era of Multigate field-effect transistors (FETs). Here, we present structural variations for Junctionless FinFET devices at the IRDS sub-5nm technology node. Four JL-FinFET novel structures are proposed, JL-MG-U-FinFET, JL-U-FinFET, JL-Inv-U-FinFET, and JL-DG-Inv-U-FinFET. The electrical and analog/RF performance of these structures are compared and it is found that JL-DG-Inv-U-FinFET gives better performance in terms of minimizing short channel effects as well as in terms of analog/radio frequency characteristics. The ION/IOFF ratio values for (JL-MG-U-FinFET, JL-U-FinFET, JL-Inv-U-FinFET, and JL-DG-Inv-U-FinFET) are observed as 8.5×106, 1.2×109, 2.04×108, and 1.1×1010, respectively. Similarly, the SS values are noted as 93.44, 70.87, 70.61, and 62.1 mV/dec for the respective configurations. The effect of variation in geometrical parameters such as gate length, U-shaped fin width, and U-shaped fin height on DC and analog/RF characteristics is also explored. It has been observed that the DC parameters such as Ion/Ioff ratio, SS are better for higher Lg, lower WU-fin, and higher HU-fin. Moreover, the JL-DG-Inv-U-FinFET-based common source amplifier produced a gain of 5.2. The results reported will aid device engineers in selecting better geometrical parameters to achieve improved JL-DG-Inv-U-FinFET performance.

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Performance analysis of metal gate engineered junctionless nanosheet fet with a ft/fmax of 224/342ghz for beyond 5g (b5g) applications

Cited by 10 publications

References 40 publications

Pushing the Boundaries: Design and Simulation Approach of Negative Capacitance Nanosheet FETs with Ferroelectric and Dielectric Spacers at the Sub-3 nm Technology Node for Analog/RF/Mixed Signal Applications

Pushing the Boundaries: Design and Simulation Approach of Negative Capacitance Nanosheet FETs with Ferroelectric and Dielectric Spacers at the Sub-3 nm Technology Node for Analog/RF/Mixed Signal Applications

Optimization of Sidewall Spacer Engineering at Sub-5 nm Technology Node For JL-Nanowire FET: Digital/Analog/RF/Circuit Perspective

Optimizing U-Shape FinFETs for Sub-5nm Technology: Performance Analysis and Device-to-Circuit Evaluation in Digital and Analog/Radio Frequency Applications

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