A novel three-layer graded SiGe strain relaxed buffer for the high crystal quality and strained Si0.5Ge0.5 layer epitaxial grown

Zhao, Zhiqian; Li, Yongliang; Wang, Guilei; Du, Anyan; Gu, Shenyan; Li, Yan; Zhang, Qingzhu; Xu, Gaobo; Ma, Xueli; Wang, Xiaolei; Yang, Hong; Luo, Jun; Li, Junfeng; Yin, Huaxiang; Wang, Wenwu

doi:10.1007/s10854-019-01779-y

Cited by 6 publications

(4 citation statements)

References 18 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…It can be found that the in situ phosphorus doping strategy did not affect the epitaxial crystalline quality, and there was approximately 1.8 μm threading dislocation (TD) defects free region within the top in situ phosphorus doped Si 0.7 Ge 0.3 SRB layer. Moreover, as with the previously developed intrinsic SiGe SRB, 8 the TD defects due to the lattice mismatch between newly developed in situ doped threelayer SiGe SRB and Si were still constrained at the bottom of SRB.…”

Section: Resultsmentioning

confidence: 59%

“…1. Compared with the standard Si channel FinFET, the main difference in the fabrication of Si 0.5 Ge 0.5 channel FinFET are as follows: first, to achieve Si 0.5 Ge 0.5 channel fabrication, before epitaxial growth of Si 0.5 Ge 0.5 layer (∼20 nm), a three-layer SiGe SRB with Ge content increasing from 10% to 30% was epitaxial grown on the Si substrate, 8 and in situ phosphorus doping was performed by adding PH 3 gas during the epitaxy of the top Si 0.7 Ge 0.3 SRB layer. Meanwhile, a chemical mechanical polishing (CMP) treatment was also used to improve the surface roughness of the three-layer SiGe SRB.…”

Section: Methodsmentioning

confidence: 99%

“…7 In our previous work, we investigated the epitaxial growth of strain relaxed buffer (SRB) layer and Si 0.5 Ge 0.5 channel introduction technique based on STI last scheme. 8,9 However, it is necessary to further overcome some other challenges, such as leakage of parasitic sub-fin channel, interface state density (Dit) of SiGe channel, and large source-drain series resistance of fin structure. [10][11][12] Therefore, for Si 0.5 Ge 0.5 channel FinFET, the fabrication of the device and its electrical characteristics optimization need to be further investigated, as relatively few studies have been reported so far.…”

mentioning

confidence: 99%

See 2 more Smart Citations

Si_0.5Ge_0.5 Channel FinFET Preparation on an In Situ Doped SiGe SRB and Its Electrical Characteristics Optimization

Chen

Li²,

Jia³

et al. 2023

ECS J. Solid State Sci. Technol.

Self Cite

View full text Add to dashboard Cite

The Si0.5Ge0.5 channel FinFET preparation on an in-situ-doped SiGe strain relaxed buffer (SRB) and its electrical characteristic optimization were explored in detail. First, an in-situ phosphorus-doped three-layer SiGe SRB was developed and a perfect Si0.5Ge0.5/Si0.7Ge0.3 SRB fin profile was achieved under the conventional STI last scheme. Then, the Si0.5Ge0.5 channel FinFET was successfully prepared according to the standard integration process of Si channel FinFET. However, it suffers bad electrical performance due to poor Si0.5Ge0.5 channel interfacial property and high S/D series resistance. Therefore, a channel passivation process including an in-situ ozone oxidation combined with HfO2/Al2O3 bi-layer gate dielectric, and a S/D silicide process are simultaneously introduced to optimize its electrical characteristics. As a result, its SS can be decreased from 174 to 104 mV/dec, and its driven current under |VGS| = |VDS| = 0.8 V can be increased from 12 to 314 μA/μm. Therefore, these newly developed technologies are practical for the Si0.5Ge0.5 channel FinFET.

show abstract

Section: Resultsmentioning

confidence: 59%

Section: Methodsmentioning

confidence: 99%

mentioning

confidence: 99%

See 1 more Smart Citation

Si_0.5Ge_0.5 Channel FinFET Preparation on an In Situ Doped SiGe SRB and Its Electrical Characteristics Optimization

Chen

Li²,

Jia³

et al. 2023

ECS J. Solid State Sci. Technol.

Self Cite

View full text Add to dashboard Cite

show abstract

“…The CMP treated three-layer SiGe SRB/Si 0.5 Ge 0.5 layer stacking structure was firstly fabricated to control the threading dislocation density. More information can be found in [10]. Then, the SiGe SRB/Si 0.5 Ge 0.5 Fin was patterned by the sidewall image transfer method using HBr-based plasma gas.…”

Section: Methodsmentioning

confidence: 99%

Fabrication technique of the Si_0.5Ge_0.5 Fin for the high mobility channel FinFET device

Zhao

Zan

et al. 2020

Semicond. Sci. Technol.

Self Cite

View full text Add to dashboard Cite

In this paper, a fabrication technique of Si 0.5 Ge 0.5 Fin for the high mobility channel FinFET device is systematically investigated. Although the shallow trench isolation (STI) densification temperature is already reduced from 1050 °C to 850 °C, the Si 0.5 Ge 0.5 Fin with the STI annealing first approach still suffers from thermal instability and micro trench issue. It is no possible to further reduce the STI densification temperature using the traditional furnace annealing for the Si 0.5 Ge 0.5 Fin, because the STI densification process of 750 °C also faces the same issue with an unacceptable STI wet etching rate. Thus, a spike annealing of 1050 °C is employed to maintain Si 0.5 Ge 0.5 Fin stability and render the STI etching rate acceptable. The spike annealing treated Si 0.5 Ge 0.5 Fin maintains a better profile than the furnace annealing sample, but it still faces the micro trench issue after the STI recess. This is because the Si 0.5 Ge 0.5 Fin is already oxidized and SiGeO x has a higher etching rate than STI oxide. Finally, a novel STI recess first process with an extra SiN capping is developed to solve both the thermal instability and the micro trench issue, and a minor Si 0.5 Ge 0.5 Fin loss with sharp Si 0.7 Ge 0.3 SRB/Si 0.5 Ge 0.5 interfaces for the STI last scheme is realized by utilizing this novel STI recess first process.

show abstract

A novel approach to Si0.5Ge0.5 channel FinFET fabrication: utilizing a three-layer SiGe strain relaxation buffer and In-Situ phosphorus doping

Li,

Luo,

Chen

et al. 2024

J Mater Sci: Mater Electron

View full text Add to dashboard Cite

A novel three-layer graded SiGe strain relaxed buffer for the high crystal quality and strained Si0.5Ge0.5 layer epitaxial grown

Cited by 6 publications

References 18 publications

Si_0.5Ge_0.5 Channel FinFET Preparation on an In Situ Doped SiGe SRB and Its Electrical Characteristics Optimization

Si_0.5Ge_0.5 Channel FinFET Preparation on an In Situ Doped SiGe SRB and Its Electrical Characteristics Optimization

Fabrication technique of the Si_0.5Ge_0.5 Fin for the high mobility channel FinFET device

A novel approach to Si0.5Ge0.5 channel FinFET fabrication: utilizing a three-layer SiGe strain relaxation buffer and In-Situ phosphorus doping

Contact Info

Product

Resources

About

A novel three-layer graded SiGe strain relaxed buffer for the high crystal quality and strained Si0.5Ge0.5 layer epitaxial grown

Cited by 6 publications

References 18 publications

Si0.5Ge0.5 Channel FinFET Preparation on an In Situ Doped SiGe SRB and Its Electrical Characteristics Optimization

Si0.5Ge0.5 Channel FinFET Preparation on an In Situ Doped SiGe SRB and Its Electrical Characteristics Optimization

Fabrication technique of the Si0.5Ge0.5 Fin for the high mobility channel FinFET device

A novel approach to Si0.5Ge0.5 channel FinFET fabrication: utilizing a three-layer SiGe strain relaxation buffer and In-Situ phosphorus doping

Contact Info

Product

Resources

About

Si_0.5Ge_0.5 Channel FinFET Preparation on an In Situ Doped SiGe SRB and Its Electrical Characteristics Optimization

Si_0.5Ge_0.5 Channel FinFET Preparation on an In Situ Doped SiGe SRB and Its Electrical Characteristics Optimization

Fabrication technique of the Si_0.5Ge_0.5 Fin for the high mobility channel FinFET device