In this paper, the optimization of SiGe interface property for SiGe channel FinFET transistor is explored in detail. First, an optimal low-temperature ozone oxidation at 300 ℃ for 30 min was confirmed based on the Al2O3/Si0.7Ge0.3 MOS capacitors. This is because that a higher oxidation temperature and a longer oxidation time could suppress the formation of GeOX in the interface layer (IL), and significantly improve interface state density (Dit). Moreover, compared with Al2O3 sample, HfO2 sample can obtain a thinner capacitance equivalent oxide thickness (CET), but it is more vulnerable to deterioration of Si0.7Ge0.3 interface property because the GeOX in the IL is more likely to diffuse into HfO2 layer. To further optimize the Dit and CET of Si0.7Ge0.3 MOS capacitor simultaneously, a stacked HfO2/Al2O3 dielectric is proposed. Compared with the HfO2 sample, its frequency dispersions characteristics and Dit have been improved significantly since the thin Al2O3 layer prevents the diffusion of GeOX to HfO2 layer and controls the growth of GeOX. Therefore, a high quality Si0.7Ge0.3 interface property optimization technology is realized by development of a low-temperature ozone oxidation (300 ℃, 30 min) combined with a stacked HfO2/Al2O3 dielectric. In addition, a Si0.7Ge0.3 FinFET utilizing this newly developed interface property optimization scheme is successfully prepared. Its excellent SS performance indicates that a good interface quality of the Si0.7Ge0.3 is obtained. The above result proves that these newly developed interface property optimization scheme is a practical technology for high mobility SiGe FinFET.

The Si0.5Ge0.5 channel FinFET preparation on an in-situ-doped SiGe strain relaxed buffer (SRB) and its electrical characteristic optimization were explored in detail. First, an in-situ phosphorus-doped three-layer SiGe SRB was developed and a perfect Si0.5Ge0.5/Si0.7Ge0.3 SRB fin profile was achieved under the conventional STI last scheme. Then, the Si0.5Ge0.5 channel FinFET was successfully prepared according to the standard integration process of Si channel FinFET. However, it suffers bad electrical performance due to poor Si0.5Ge0.5 channel interfacial property and high S/D series resistance. Therefore, a channel passivation process including an in-situ ozone oxidation combined with HfO2/Al2O3 bi-layer gate dielectric, and a S/D silicide process are simultaneously introduced to optimize its electrical characteristics. As a result, its SS can be decreased from 174 to 104 mV/dec, and its driven current under |VGS| = |VDS| = 0.8 V can be increased from 12 to 314 μA/μm. Therefore, these newly developed technologies are practical for the Si0.5Ge0.5 channel FinFET.